From patchwork Sun Feb 2 23:17:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 24020 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f69.google.com (mail-oa0-f69.google.com [209.85.219.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1949720341 for ; Sun, 2 Feb 2014 23:17:37 +0000 (UTC) Received: by mail-oa0-f69.google.com with SMTP id h16sf28225816oag.0 for ; Sun, 02 Feb 2014 15:17:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=CFCUOxGvdRB6x61OuyKeE5DjcVBc9VUTQsxBvj9zErE=; b=bjBzy8LsNCVkOuBbWV8XYP1bBPEl4dp9ThipJBpDsF5K6CEZmC9EKMgIhFVs1Ba5qa sY8AzsivTGwhr+IoKR0OiwXZfFiBJtUf3oeSBoK/XUfnCEq9dT1EEpQdmUVqHLpG19X7 NZfN9sXwIJQO3Nh6UrzF1qQXJ6UB2n1TkpU8z7zRwrHrTatJuyGJbqG5Xx3qaH0raXlD dwZPPiHrS+8ZjHZJraH3uZpFBRRo4Vp6aOtCnwIK85HVLWWnpuhsF4ITXc/alWucEneA f/C26X+P0hnPVgP4Fs5f+hgBAmObvmfleQryPog3WNIR0d24nzocoj2Ev0vDeTc8E9rX qyrg== X-Gm-Message-State: ALoCoQmWL2EMNVbhwSPvfGQTvuXBiiuBDGTDiT9MTUiCNbRgr9rGeCmlt2NEuzk53ig/vcBG7wXY X-Received: by 10.182.66.193 with SMTP id h1mr811395obt.47.1391383057193; Sun, 02 Feb 2014 15:17:37 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.29.102 with SMTP id a93ls1636256qga.33.gmail; Sun, 02 Feb 2014 15:17:37 -0800 (PST) X-Received: by 10.220.2.199 with SMTP id 7mr26004292vck.4.1391383057097; Sun, 02 Feb 2014 15:17:37 -0800 (PST) Received: from mail-ve0-f176.google.com (mail-ve0-f176.google.com [209.85.128.176]) by mx.google.com with ESMTPS id b2si6239682vcy.85.2014.02.02.15.17.37 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 02 Feb 2014 15:17:37 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.176; Received: by mail-ve0-f176.google.com with SMTP id oz11so4452147veb.35 for ; Sun, 02 Feb 2014 15:17:37 -0800 (PST) X-Received: by 10.220.124.65 with SMTP id t1mr920944vcr.26.1391383057014; Sun, 02 Feb 2014 15:17:37 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp117662vcz; Sun, 2 Feb 2014 15:17:36 -0800 (PST) X-Received: by 10.69.0.39 with SMTP id av7mr33778530pbd.4.1391383055979; Sun, 02 Feb 2014 15:17:35 -0800 (PST) Received: from mail-pd0-f176.google.com (mail-pd0-f176.google.com [209.85.192.176]) by mx.google.com with ESMTPS id to9si18389441pbc.35.2014.02.02.15.17.35 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 02 Feb 2014 15:17:35 -0800 (PST) Received-SPF: neutral (google.com: 209.85.192.176 is neither permitted nor denied by best guess record for domain of christoffer.dall@linaro.org) client-ip=209.85.192.176; Received: by mail-pd0-f176.google.com with SMTP id w10so6172746pde.21 for ; Sun, 02 Feb 2014 15:17:35 -0800 (PST) X-Received: by 10.66.194.2 with SMTP id hs2mr33545181pac.79.1391383055608; Sun, 02 Feb 2014 15:17:35 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id qq5sm49777615pbb.24.2014.02.02.15.17.33 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 02 Feb 2014 15:17:34 -0800 (PST) From: Christoffer Dall To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, patches@linaro.org, Christoffer Dall Subject: [PATCH v6 5/6] arm_gic: Add GICC_APRn state to the GICState Date: Sun, 2 Feb 2014 15:17:23 -0800 Message-Id: <1391383044-596-6-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1391383044-596-1-git-send-email-christoffer.dall@linaro.org> References: <1391383044-596-1-git-send-email-christoffer.dall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The GICC_APRn registers are not currently supported by the ARM GIC v2.0 emulation. This patch adds the missing state. Note that we also change the number of APRs to use a define GIC_NR_APRS based on the maximum number of preemption levels. This patch also adds RAZ/WI accessors for the four registers on the emulated CPU interface. Reviewed-by: Peter Maydell Signed-off-by: Christoffer Dall --- Changes [v4 -> v5]: - Add TODO comment about reworking last_active and running_irq to use te new field instead. Changes [v3 -> v4]: - Fixed grammatical error and use qemu_log_mask for print. hw/intc/arm_gic.c | 5 +++++ hw/intc/arm_gic_common.c | 5 +++-- include/hw/intc/arm_gic_common.h | 19 +++++++++++++++++++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 5413a24..93eaa6b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -678,6 +678,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) return s->current_pending[cpu]; case 0x1c: /* Aliased Binary Point */ return s->abpr[cpu]; + case 0xd0: case 0xd4: case 0xd8: case 0xdc: + return s->apr[(offset - 0xd0) / 4][cpu]; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); @@ -705,6 +707,9 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) s->abpr[cpu] = (value & 0x7); } break; + case 0xd0: case 0xd4: case 0xd8: case 0xdc: + qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n"); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index d2d8ce1..6d884ec 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -58,8 +58,8 @@ static const VMStateDescription vmstate_gic_irq_state = { static const VMStateDescription vmstate_gic = { .name = "arm_gic", - .version_id = 6, - .minimum_version_id = 6, + .version_id = 7, + .minimum_version_id = 7, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { @@ -78,6 +78,7 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), + VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_END_OF_LIST() } }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 0f0644b..f6887ed 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -31,6 +31,9 @@ /* Maximum number of possible CPU interfaces, determined by GIC architecture */ #define GIC_NCPU 8 +#define MAX_NR_GROUP_PRIO 128 +#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) + typedef struct gic_irq_state { /* The enable bits are only banked for per-cpu interrupts. */ uint8_t enabled; @@ -75,6 +78,22 @@ typedef struct GICState { uint8_t bpr[GIC_NCPU]; uint8_t abpr[GIC_NCPU]; + /* The APR is implementation defined, so we choose a layout identical to + * the KVM ABI layout for QEMU's implementation of the gic: + * If an interrupt for preemption level X is active, then + * APRn[X mod 32] == 0b1, where n = X / 32 + * otherwise the bit is clear. + * + * TODO: rewrite the interrupt acknowlege/complete routines to use + * the APR registers to track the necessary information to update + * s->running_priority[] on interrupt completion (ie completely remove + * last_active[][] and running_irq[]). This will be necessary if we ever + * want to support TCG<->KVM migration, or TCG guests which can + * do power management involving powering down and restarting + * the GIC. + */ + uint32_t apr[GIC_NR_APRS][GIC_NCPU]; + uint32_t num_cpu; MemoryRegion iomem; /* Distributor */