From patchwork Thu Mar 6 19:32:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 25844 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f72.google.com (mail-oa0-f72.google.com [209.85.219.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9080D203C3 for ; Thu, 6 Mar 2014 19:33:32 +0000 (UTC) Received: by mail-oa0-f72.google.com with SMTP id g12sf11553317oah.3 for ; Thu, 06 Mar 2014 11:33:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=R6NxVnvkkiocikR8npmU501hXn0thvEZz9BitU/pHkg=; b=Q+1ieHk7W9CF7mmq91wD6je5XCAfujvArrnNAEYwz6yYQ/IK+pTLuPFSzQW7nYYxAd 1X8rHqJOK9dpofv/BsXtWmvweOkaep95tMAEg1T014dXOutwGkFWv6bv1QVawARkAHwG 8IRktsWaoub6wqH2UN82kCYFknirnyYv32gL0DI2lWMfkg2v0Jmabpd1VnstZnZ2nkh+ LdK4wUnJFl7cPHZvQ8PjaVPZXfqNjSHJosmkLBDVdDNdlvf+a06Wfdj4pjaYcvtclxb+ Yvuq4YWHecxxHgfvhrvHurxfJiZTkLXZ0Tx2E5tSgUmaQmu36hD8Ca7ymdAm6+Rnw2rZ 0Cyg== X-Gm-Message-State: ALoCoQkt+PX2qYEEqHMkMe4fpsKZJKiaJi1HfNy+Yn87czUPqrn2HFlHqiM4gMMRx9dXG+vssgsH X-Received: by 10.42.107.146 with SMTP id d18mr5109083icp.8.1394134412168; Thu, 06 Mar 2014 11:33:32 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.26.35 with SMTP id 32ls893185qgu.80.gmail; Thu, 06 Mar 2014 11:33:31 -0800 (PST) X-Received: by 10.220.11.141 with SMTP id t13mr2091706vct.30.1394134411961; Thu, 06 Mar 2014 11:33:31 -0800 (PST) Received: from mail-ve0-f181.google.com (mail-ve0-f181.google.com [209.85.128.181]) by mx.google.com with ESMTPS id rq10si1420998vcb.24.2014.03.06.11.33.31 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Mar 2014 11:33:31 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.181; Received: by mail-ve0-f181.google.com with SMTP id oy12so3102552veb.40 for ; Thu, 06 Mar 2014 11:33:31 -0800 (PST) X-Received: by 10.58.91.101 with SMTP id cd5mr6489592veb.5.1394134411872; Thu, 06 Mar 2014 11:33:31 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.78.9 with SMTP id i9csp61903vck; Thu, 6 Mar 2014 11:33:31 -0800 (PST) X-Received: by 10.194.58.19 with SMTP id m19mr12985498wjq.30.1394134407658; Thu, 06 Mar 2014 11:33:27 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id o15si6210811wjr.159.2014.03.06.11.33.27 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 06 Mar 2014 11:33:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WLe2T-0000SS-8h; Thu, 06 Mar 2014 19:33:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite , Rob Herring Subject: [PATCH v4 02/21] target-arm: Implement AArch64 DAIF system register Date: Thu, 6 Mar 2014 19:32:46 +0000 Message-Id: <1394134385-1727-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> References: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Implement the DAIF system register which is a view of the DAIF bits in PSTATE. To avoid needing a readfn, we widen the daif field in CPUARMState to uint64_t. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/cpu.h | 2 +- target-arm/helper.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6252ff3..45eb6a2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -160,7 +160,7 @@ typedef struct CPUARMState { uint32_t GE; /* cpsr[19:16] */ uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ - uint32_t daif; /* exception masks, in the bits they are in in PSTATE */ + uint64_t daif; /* exception masks, in the bits they are in in PSTATE */ /* System control coprocessor (cp15) */ struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index 3d65bae..f7168c1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1593,6 +1593,20 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, vfp_set_fpsr(env, value); } +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) +{ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->daif = value & PSTATE_DAIF; +} + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -1636,6 +1650,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "NZCV", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, .access = PL0_RW, .type = ARM_CP_NZCV }, + { .name = "DAIF", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, + .type = ARM_CP_NO_MIGRATE, + .access = PL0_RW, .accessfn = aa64_daif_access, + .fieldoffset = offsetof(CPUARMState, daif), + .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, { .name = "FPCR", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },