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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id t1si6362692wjx.67.2014.03.06.11.56.59 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 06 Mar 2014 11:57:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WLe2T-0000Si-GR; Thu, 06 Mar 2014 19:33:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite , Rob Herring Subject: [PATCH v4 06/21] target-arm: Provide syndrome information for MMU faults Date: Thu, 6 Mar 2014 19:32:50 +0000 Message-Id: <1394134385-1727-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> References: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Rob Herring Set up the required syndrome information when we detect an MMU fault. Signed-off-by: Rob Herring [PMM: split out from exception handling patch, tweaked to bring in line with how we create other kinds of syndrome information] Signed-off-by: Peter Maydell --- target-arm/helper.c | 16 ++++++++++++++++ target-arm/internals.h | 13 +++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 2fa01ae..d547a9d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3586,6 +3586,7 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, target_ulong page_size; int prot; int ret, is_user; + uint32_t syn; is_user = mmu_idx == MMU_USER_IDX; ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, @@ -3598,14 +3599,29 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, return 0; } + /* AArch64 syndrome does not have an LPAE bit */ + syn = ret & ~(1 << 9); + + /* For insn and data aborts we assume there is no instruction syndrome + * information; this is always true for exceptions reported to EL1. + */ if (access_type == 2) { + syn = syn_insn_abort(0, 0, syn); env->exception_index = EXCP_PREFETCH_ABORT; } else { + syn = syn_data_abort(0, 0, 0, access_type == 1, syn); if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) { ret |= (1 << 11); } env->exception_index = EXCP_DATA_ABORT; } + + /* Set bit 26 for exceptions with no change in EL */ + if (arm_current_pl(env)) { + syn |= 1 << ARM_EL_EC_SHIFT; + } + + env->exception.syndrome = syn; env->exception.vaddress = address; env->exception.fsr = ret; return 1; diff --git a/target-arm/internals.h b/target-arm/internals.h index 9bec4e1..93f56a5 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -188,4 +188,17 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; } +static inline uint32_t syn_insn_abort(int ea, int s1ptw, int fsc) +{ + return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (ea << 9) + | (s1ptw << 7) | fsc; +} + +static inline uint32_t syn_data_abort(int ea, int cm, int s1ptw, int wnr, + int fsc) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (ea << 9) + | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; +} + #endif