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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id fs14si19514029wjc.134.2014.03.10.12.10.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 10 Mar 2014 12:10:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WN5b7-0002Sz-2L; Mon, 10 Mar 2014 19:10:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-trivial@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 01/12] target-i386: Avoid shifting left into sign bit Date: Mon, 10 Mar 2014 19:10:37 +0000 Message-Id: <1394478649-9453-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1394478649-9453-1-git-send-email-peter.maydell@linaro.org> References: <1394478649-9453-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add 'U' suffixes where necessary to avoid (1 << 31) which shifts left into the sign bit, which is undefined behaviour. Signed-off-by: Peter Maydell --- target-i386/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 0014acc..064f987 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -202,7 +202,7 @@ #define CR0_NE_MASK (1 << 5) #define CR0_WP_MASK (1 << 16) #define CR0_AM_MASK (1 << 18) -#define CR0_PG_MASK (1 << 31) +#define CR0_PG_MASK (1U << 31) #define CR4_VME_MASK (1 << 0) #define CR4_PVI_MASK (1 << 1) @@ -436,7 +436,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_HT (1 << 28) #define CPUID_TM (1 << 29) #define CPUID_IA64 (1 << 30) -#define CPUID_PBE (1 << 31) +#define CPUID_PBE (1U << 31) #define CPUID_EXT_SSE3 (1 << 0) #define CPUID_EXT_PCLMULQDQ (1 << 1) @@ -467,7 +467,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_EXT_AVX (1 << 28) #define CPUID_EXT_F16C (1 << 29) #define CPUID_EXT_RDRAND (1 << 30) -#define CPUID_EXT_HYPERVISOR (1 << 31) +#define CPUID_EXT_HYPERVISOR (1U << 31) #define CPUID_EXT2_FPU (1 << 0) #define CPUID_EXT2_VME (1 << 1) @@ -496,7 +496,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_EXT2_RDTSCP (1 << 27) #define CPUID_EXT2_LM (1 << 29) #define CPUID_EXT2_3DNOWEXT (1 << 30) -#define CPUID_EXT2_3DNOW (1 << 31) +#define CPUID_EXT2_3DNOW (1U << 31) /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \