From patchwork Tue May 13 15:31:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 30078 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f200.google.com (mail-ve0-f200.google.com [209.85.128.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0C91020446 for ; Tue, 13 May 2014 15:45:03 +0000 (UTC) Received: by mail-ve0-f200.google.com with SMTP id pa12sf1555249veb.3 for ; Tue, 13 May 2014 08:45:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=dY38AwzvxvGBhcX1Vq4fs5jP/Z8DMitJoVnnDrm0tLQ=; b=TQqT7OVhBpwWM/hJJtapfqRPPnbw76+hbZP06G1Chdg43Decd1jsNY+zSxVtiEzlek GMsNXrLvMkvjy8XMiQOHVem516mm5GNWdQ7ZFSfv86pvpzAgcDP0Ded6LqBHeNu2V3b3 ldSEVpGK7oaIDYqqk0g3Ilf+HgEIkxtR/+qFECQzkOwde4pZPntpCS/nf8JA3WvLR1jz 7rhpPxHan0wTlGdYH6P8PN6nadD/oMWocMhY2x6UMTL1vStOQUZPzmURYcaCq4QDbfOu FnLgYkgwve8A2qpfoP7mKxN6r/CGdNmhw/LwPDQ19GGV02a+0+cfWoJM1NeOKz7QwfBh aPZA== X-Gm-Message-State: ALoCoQnCpvK5ZX6MaHjWQCFBYfOmrUMoOHllrpm1cUYnngdYsXiajn5K9SJboJsA0YfgMgr1NU1X X-Received: by 10.58.106.229 with SMTP id gx5mr17385336veb.22.1399995902698; Tue, 13 May 2014 08:45:02 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.46.53 with SMTP id j50ls1985927qga.67.gmail; Tue, 13 May 2014 08:45:02 -0700 (PDT) X-Received: by 10.52.164.175 with SMTP id yr15mr757283vdb.59.1399995902554; Tue, 13 May 2014 08:45:02 -0700 (PDT) Received: from mail-ve0-f176.google.com (mail-ve0-f176.google.com [209.85.128.176]) by mx.google.com with ESMTPS id ph6si2718803veb.53.2014.05.13.08.45.02 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 13 May 2014 08:45:02 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.176 as permitted sender) client-ip=209.85.128.176; Received: by mail-ve0-f176.google.com with SMTP id jz11so680592veb.21 for ; Tue, 13 May 2014 08:45:02 -0700 (PDT) X-Received: by 10.220.191.134 with SMTP id dm6mr29985987vcb.16.1399995902446; Tue, 13 May 2014 08:45:02 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp161403vcb; Tue, 13 May 2014 08:45:01 -0700 (PDT) X-Received: by 10.194.62.234 with SMTP id b10mr8629133wjs.48.1399995901072; Tue, 13 May 2014 08:45:01 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id cv1si3987680wib.71.2014.05.13.08.45.00 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 13 May 2014 08:45:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:45895 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkEkU-0005TL-5X for patch@linaro.org; Tue, 13 May 2014 11:36:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkEgL-00083S-P2 for qemu-devel@nongnu.org; Tue, 13 May 2014 11:31:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkEgH-00069I-C4 for qemu-devel@nongnu.org; Tue, 13 May 2014 11:31:53 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48125) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkEgG-00066p-VL for qemu-devel@nongnu.org; Tue, 13 May 2014 11:31:49 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WkEg7-0006xN-TF; Tue, 13 May 2014 16:31:39 +0100 From: Peter Maydell To: Anthony Liguori Date: Tue, 13 May 2014 16:31:36 +0100 Message-Id: <1399995099-26635-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1399995099-26635-1-git-send-email-peter.maydell@linaro.org> References: <1399995099-26635-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PULL 14/17] hw/dma/omap_dma: Add (uint32_t) casts when shifting uint16_t by 16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add missing (uint32_t) casts in cases where we're trying to put a uint16_t value into the top half of a 32-bit field. These were already present in some but not all places. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- hw/dma/omap_dma.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index 0e8cccd..0f35c42 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -973,7 +973,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, case 0x22: /* DMA_COLOR_U */ ch->color &= 0xffff; - ch->color |= value << 16; + ch->color |= (uint32_t)value << 16; break; case 0x24: /* DMA_CCR2 */ @@ -1043,7 +1043,7 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, case 0xbca: /* TOP_B1_U */ s->src_f1_top &= 0x0000ffff; - s->src_f1_top |= value << 16; + s->src_f1_top |= (uint32_t)value << 16; break; case 0xbcc: /* BOT_B1_L */ @@ -1265,7 +1265,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ s->src_f1_top &= 0x0000ffff; - s->src_f1_top |= value << 16; + s->src_f1_top |= (uint32_t)value << 16; break; case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ @@ -1275,7 +1275,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ s->src_f1_bottom &= 0x0000ffff; - s->src_f1_bottom |= value << 16; + s->src_f1_bottom |= (uint32_t)value << 16; break; case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ @@ -1285,7 +1285,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ s->src_f2_top &= 0x0000ffff; - s->src_f2_top |= value << 16; + s->src_f2_top |= (uint32_t)value << 16; break; case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ @@ -1295,7 +1295,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ s->src_f2_bottom &= 0x0000ffff; - s->src_f2_bottom |= value << 16; + s->src_f2_bottom |= (uint32_t)value << 16; break; default: