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Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 25 May 2014 11:08:31 +1000 Message-Id: <1400980132-25949-3-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> References: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::235 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, greg.bellows@linaro.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v5 02/23] target-arm/translate.c: Clean up mmu index handling for ldrt/strt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Original-Sender: edgar.iglesias@gmail.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::233 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=fail header.i=@gmail.com; dmarc=fail (p=NONE dis=NONE) header.from=gmail.com Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Peter Maydell Clean up the mmu index handling for ldrt/strt insns: instead of a flag 'user' indicating whether to treat the store as user mode or not, use 'memidx' to indicate the correct memory index to use. Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- target-arm/translate.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index a4d920b..e708f4a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8568,7 +8568,12 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; tmp2 = load_reg(s, rn); - i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000); + if ((insn & 0x01200000) == 0x00200000) { + /* ldrt/strt */ + i = MMU_USER_IDX; + } else { + i = get_mem_index(s); + } if (insn & (1 << 24)) gen_add_data_offset(s, insn, tmp2); if (insn & (1 << 20)) { @@ -9841,7 +9846,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw { int postinc = 0; int writeback = 0; - int user; + int memidx; if ((insn & 0x01100000) == 0x01000000) { if (disas_neon_ls_insn(env, s, insn)) goto illegal_op; @@ -9885,7 +9890,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw return 1; } } - user = IS_USER(s); + memidx = get_mem_index(s); if (rn == 15) { addr = tcg_temp_new_i32(); /* PC relative. */ @@ -9922,7 +9927,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw break; case 0xe: /* User privilege. */ tcg_gen_addi_i32(addr, addr, imm); - user = 1; + memidx = MMU_USER_IDX; break; case 0x9: /* Post-decrement. */ imm = -imm; @@ -9949,19 +9954,19 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp = tcg_temp_new_i32(); switch (op) { case 0: - gen_aa32_ld8u(tmp, addr, user); + gen_aa32_ld8u(tmp, addr, memidx); break; case 4: - gen_aa32_ld8s(tmp, addr, user); + gen_aa32_ld8s(tmp, addr, memidx); break; case 1: - gen_aa32_ld16u(tmp, addr, user); + gen_aa32_ld16u(tmp, addr, memidx); break; case 5: - gen_aa32_ld16s(tmp, addr, user); + gen_aa32_ld16s(tmp, addr, memidx); break; case 2: - gen_aa32_ld32u(tmp, addr, user); + gen_aa32_ld32u(tmp, addr, memidx); break; default: tcg_temp_free_i32(tmp); @@ -9978,13 +9983,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp = load_reg(s, rs); switch (op) { case 0: - gen_aa32_st8(tmp, addr, user); + gen_aa32_st8(tmp, addr, memidx); break; case 1: - gen_aa32_st16(tmp, addr, user); + gen_aa32_st16(tmp, addr, memidx); break; case 2: - gen_aa32_st32(tmp, addr, user); + gen_aa32_st32(tmp, addr, memidx); break; default: tcg_temp_free_i32(tmp);