From patchwork Tue May 27 16:28:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 31014 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f71.google.com (mail-yh0-f71.google.com [209.85.213.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 3C726203C3 for ; Tue, 27 May 2014 17:14:04 +0000 (UTC) Received: by mail-yh0-f71.google.com with SMTP id 29sf40813048yhl.2 for ; Tue, 27 May 2014 10:14:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=LTnfngUYjHU6JKzIgmIPbVuF2ScVc1en9X3FiarbC+w=; b=JPd/FN6RFF6FGly/ojgQmW7quvlHE03pWus0lFTOQzSO3/+I2nLHZWqZVo/clIpFoj NjTcaMTCXV6MC15ayIEcz2IcljcwC02L6TGj9ucQYA81nfQT0GAMqLlIcJpaozKAA2an T2iixxPnpbAO2O7KPOVqXq69XTjga94FopvNEpdcKdHmvPROxV+gDWdlVPVqjKXKWYUO bU5nDk1g7p21d8pXsHJoo7ldcQ4VI9g2n2hFOn20FAVETLm6zxUY9Iz1zHXNQnjtAjPH qH+h1iVjq+ymYTbvk/GGoS0vQA+2EuuoOwuiZyC/opfkvvnRQJF6wSpkux6JmUnPLAKu TP+w== X-Gm-Message-State: ALoCoQkhTTTlEoxVBU2iTXV5wS6w4aKjVs8BC47CMYl9zHn/vPGNq3OnUim5EnI88goz4T6aHN+j X-Received: by 10.58.234.164 with SMTP id uf4mr13599739vec.13.1401210844022; Tue, 27 May 2014 10:14:04 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.87.141 with SMTP id r13ls3307650qgd.98.gmail; Tue, 27 May 2014 10:14:03 -0700 (PDT) X-Received: by 10.58.46.231 with SMTP id y7mr28596470vem.5.1401210843893; Tue, 27 May 2014 10:14:03 -0700 (PDT) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by mx.google.com with ESMTPS id fe3si8569231vec.43.2014.05.27.10.14.03 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 27 May 2014 10:14:03 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.173 as permitted sender) client-ip=209.85.128.173; Received: by mail-ve0-f173.google.com with SMTP id pa12so10972060veb.4 for ; Tue, 27 May 2014 10:14:03 -0700 (PDT) X-Received: by 10.58.216.163 with SMTP id or3mr2168051vec.80.1401210843814; Tue, 27 May 2014 10:14:03 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp135808vcb; Tue, 27 May 2014 10:14:03 -0700 (PDT) X-Received: by 10.224.0.70 with SMTP id 6mr15882014qaa.100.1401210842800; Tue, 27 May 2014 10:14:02 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n7si18341054qas.81.2014.05.27.10.14.02 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 27 May 2014 10:14:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:36522 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpKJR-0002yc-P7 for patch@linaro.org; Tue, 27 May 2014 12:33:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41443) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpKF4-00037s-FC for qemu-devel@nongnu.org; Tue, 27 May 2014 12:28:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WpKF3-0002q1-NI for qemu-devel@nongnu.org; Tue, 27 May 2014 12:28:46 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48252) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpKF3-0002lf-HG for qemu-devel@nongnu.org; Tue, 27 May 2014 12:28:45 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WpKEt-0005rW-CN; Tue, 27 May 2014 17:28:35 +0100 From: Peter Maydell To: Anthony Liguori Date: Tue, 27 May 2014 17:28:27 +0100 Message-Id: <1401208114-22404-20-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1401208114-22404-1-git-send-email-peter.maydell@linaro.org> References: <1401208114-22404-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PULL 19/26] target-arm: Register EL3 versions of ELR and SPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias Message-id: 1400980132-25949-17-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index a49cf94..e0f3bb8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2114,6 +2114,19 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v8_el3_cp_reginfo[] = { + { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, + { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2368,6 +2381,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, v8_el2_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new * PMSA core later than the ARM946 will require that we