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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id yq5si8785645wjc.37.2014.05.30.07.10.25 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 30 May 2014 07:10:26 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WqNHJ-0007Hu-7x; Fri, 30 May 2014 14:55:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Ard Biesheuvel , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 3/9] target-arm: Clean up handling of ARMv8 optional feature bits Date: Fri, 30 May 2014 14:55:19 +0100 Message-Id: <1401458125-27977-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1401458125-27977-1-git-send-email-peter.maydell@linaro.org> References: <1401458125-27977-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , CRC and crypto are both optional v8 extensions, so FEATURE_V8 should not imply them. Instead we should set these bits in the initfns for the 32-bit and 64-bit "cpu any" and for the Cortex-A57. Signed-off-by: Peter Maydell --- target-arm/cpu.c | 8 ++++---- target-arm/cpu64.c | 10 ++++++++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 383e22a..bc19d80 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -316,10 +316,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_ARM_DIV); set_feature(env, ARM_FEATURE_LPAE); - set_feature(env, ARM_FEATURE_V8_AES); - set_feature(env, ARM_FEATURE_V8_SHA1); - set_feature(env, ARM_FEATURE_V8_SHA256); - set_feature(env, ARM_FEATURE_V8_PMULL); } if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); @@ -960,6 +956,10 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->midr = 0xffffffff; } diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index c151dea..0e89265 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -98,6 +98,11 @@ static void aarch64_a57_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; cpu->midr = 0x411fd070; cpu->reset_fpsid = 0x41034070; @@ -140,6 +145,11 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }