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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id s78si9751539qgd.19.2014.07.31.06.30.04 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 31 Jul 2014 06:30:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:56736 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XCqQm-0006I1-Jy for patch@linaro.org; Thu, 31 Jul 2014 09:30:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51612) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XCq4I-00008m-Ec for qemu-devel@nongnu.org; Thu, 31 Jul 2014 09:06:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XCq49-0001FD-Eb for qemu-devel@nongnu.org; Thu, 31 Jul 2014 09:06:50 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:50106 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XCq49-0001Ez-5E for qemu-devel@nongnu.org; Thu, 31 Jul 2014 09:06:41 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaro.local) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1XCqE0-0002HE-03; Thu, 31 Jul 2014 15:16:52 +0200 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Thu, 31 Jul 2014 14:06:31 +0100 Message-Id: <1406811992-6766-9-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.0.3 In-Reply-To: <1406811992-6766-1-git-send-email-alex.bennee@linaro.org> References: <1406811992-6766-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , l@dorileo.org, Richard Henderson Subject: [Qemu-devel] [PATCH v3 8/9] qemu-log: dfilter-ise exec, out_asm, and op_opt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This ensures the code generation debug code will honour -dfilter if set. For the "exec" tracing I've added a new inline macro for efficiency's sake. I've not touched CPU_LOG_TB_OP as this is buried in each individual target. Signed-off-by: Alex Bennée ---- v2 - checkpatch updates - add qemu_log_mask_and_addr macro for inline dump for traces - re-base on re-factored tcg layout - include new Trace & Link lines diff --git a/cpu-exec.c b/cpu-exec.c index b7786fe..2d51c1e 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -49,8 +49,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) uintptr_t next_tb; uint8_t *tb_ptr = itb->tc_ptr; - qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n", - itb->tc_ptr, itb->pc, lookup_symbol(itb->pc)); + qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, + "Trace %p [" TARGET_FMT_lx "] %s\n", + itb->tc_ptr, itb->pc, lookup_symbol(itb->pc)); #if defined(DEBUG_DISAS) if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { @@ -76,10 +77,10 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) */ CPUClass *cc = CPU_GET_CLASS(cpu); TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); - qemu_log_mask(CPU_LOG_EXEC, - "Abandoned execution of TB chain before %p [" - TARGET_FMT_lx "] %s\n", - itb->tc_ptr, itb->pc, lookup_symbol(itb->pc)); + qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, + "Abandoned execution of TB chain before %p [" + TARGET_FMT_lx "] %s\n", + itb->tc_ptr, itb->pc, lookup_symbol(itb->pc)); if (cc->synchronize_from_tb) { cc->synchronize_from_tb(cpu, tb); } else { diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2ff6a6b..52b4143 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -297,9 +297,11 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, { /* NOTE: this test is only needed for thread safety */ if (!tb->jmp_next[n]) { - qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p [" TARGET_FMT_lx - "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc_ptr, tb->pc, n, tb_next->tc_ptr, tb_next->pc); + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, + "Linking TBs %p [" TARGET_FMT_lx + "] index %d -> %p [" TARGET_FMT_lx "]\n", + tb->tc_ptr, tb->pc, n, + tb_next->tc_ptr, tb_next->pc); /* patch the native jump address */ tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); diff --git a/include/qemu/log.h b/include/qemu/log.h index 8cfe57f..f6cef9e 100644 --- a/include/qemu/log.h +++ b/include/qemu/log.h @@ -76,6 +76,21 @@ qemu_log_vprintf(const char *fmt, va_list va) } \ } while (0) +/* log only if a bit is set on the current loglevel mask + * and we are in the address range we care about: + * @mask: bit to check in the mask + * @addr: address to check in dfilter + * @fmt: printf-style format string + * @args: optional arguments for format string + */ +#define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \ + do { \ + if (unlikely(qemu_loglevel_mask(MASK)) && \ + qemu_log_in_addr_range(ADDR)) { \ + qemu_log(FMT, ## __VA_ARGS__); \ + } \ + } while (0) + /* Special cases: */ /* cpu_dump_state() logging functions: */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 1ed085c..732cec4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2427,7 +2427,8 @@ static inline int tcg_gen_code_common(TCGContext *s, TranslationBlock *tb, g_assert(tb->tc_size == 0 || search_pc > 0); #ifdef DEBUG_DISAS - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) + && qemu_log_in_addr_range(tb->pc))) { qemu_log("OP:\n"); tcg_dump_ops(s); qemu_log("\n"); @@ -2455,7 +2456,8 @@ static inline int tcg_gen_code_common(TCGContext *s, TranslationBlock *tb, #endif #ifdef DEBUG_DISAS - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) + && qemu_log_in_addr_range(tb->pc))) { qemu_log("OP after optimization and liveness analysis:\n"); tcg_dump_ops(s); qemu_log("\n"); @@ -2478,11 +2480,6 @@ static inline int tcg_gen_code_common(TCGContext *s, TranslationBlock *tb, tcg_table_op_count[opc]++; #endif def = &tcg_op_defs[opc]; -#if 0 - printf("%s: %d %d %d\n", def->name, - def->nb_oargs, def->nb_iargs, def->nb_cargs); - // dump_regs(s); -#endif switch(opc) { case INDEX_op_mov_i32: case INDEX_op_mov_i64: diff --git a/translate-all.c b/translate-all.c index 402112c..4809840 100644 --- a/translate-all.c +++ b/translate-all.c @@ -199,7 +199,8 @@ void cpu_gen_code(CPUArchState *env, TranslationBlock *tb) tb_write_perfmap(tb->tc_ptr, tb->tc_size, tb->pc); #ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { + if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && + qemu_log_in_addr_range(tb->pc)) { qemu_log("OUT: [size=%d]\n", tb->tc_size); log_disas(tb->tc_ptr, tb->tc_size); qemu_log("\n");