From patchwork Fri Oct 10 16:49:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 38627 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f70.google.com (mail-ee0-f70.google.com [74.125.83.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D733D202DB for ; Fri, 10 Oct 2014 17:14:26 +0000 (UTC) Received: by mail-ee0-f70.google.com with SMTP id c13sf2458931eek.5 for ; Fri, 10 Oct 2014 10:14:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=bxlhow4HnISZUi/LC3jsw2g3t+lxE2lYjn7or2tr2IM=; b=jl9xYq18rji4vIGqGQvMs3ICws8fgyBQlP89BwBxbyjdukLdMwUsd4FR5DIT0jqwCk n+Lmi3O4TwWtscpjXw8d9KXjfECX+QAKljRWiF2Mz/cZxirvVIyFgKpB4mHv6eXOgPHj nHu7g7I5BKcGgLw7UWaOx3MrbU/IJ1x27usSBGbkI0rT7iBDrj+TlEGAF4c96LjuT8Ja 8UDqC2IzmfnLKeceR0g6UcncKOrHFKdx67XDnTBcCVP6Iwx79y3btEt356U0ZT4BRKmF HcU/lTx/amlRFn3RiHboXvZPU40Qxms1l+Cz6cPJQHpVWA8rKNKsO65fNrTf9XZ3kM43 7wHg== X-Gm-Message-State: ALoCoQnhITzyb3rRZryXuZnyD80XnnUL/wd/kY1YVLjkEFmvUlMU6CZ/ACseBA//Zntfe28XAgxL X-Received: by 10.112.151.3 with SMTP id um3mr19210lbb.15.1412961265700; Fri, 10 Oct 2014 10:14:25 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.20.42 with SMTP id k10ls287550lae.66.gmail; Fri, 10 Oct 2014 10:14:25 -0700 (PDT) X-Received: by 10.112.205.39 with SMTP id ld7mr6098620lbc.40.1412959796746; Fri, 10 Oct 2014 09:49:56 -0700 (PDT) Received: from mail-la0-f49.google.com (mail-la0-f49.google.com [209.85.215.49]) by mx.google.com with ESMTPS id pd3si9933777lbc.80.2014.10.10.09.49.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:49:55 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) client-ip=209.85.215.49; Received: by mail-la0-f49.google.com with SMTP id q1so3591650lam.8 for ; Fri, 10 Oct 2014 09:49:55 -0700 (PDT) X-Received: by 10.112.62.200 with SMTP id a8mr6091882lbs.34.1412959795485; Fri, 10 Oct 2014 09:49:55 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.84.229 with SMTP id c5csp463331lbz; Fri, 10 Oct 2014 09:49:55 -0700 (PDT) X-Received: by 10.180.85.41 with SMTP id e9mr6079512wiz.21.1412959794855; Fri, 10 Oct 2014 09:49:54 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ga5si4136159wib.25.2014.10.10.09.49.54 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:49:54 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XcdO4-0005OT-6k; Fri, 10 Oct 2014 17:49:52 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Christopher Covington Subject: [PATCH] target-arm: Correct sense of the DCZID DZP bit Date: Fri, 10 Oct 2014 17:49:52 +0100 Message-Id: <1412959792-20708-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The DZP bit in the DCZID system register should be set if the control bits which prohibit use of the DC ZVA instruction have been set (it stands for Data Zero Prohibited). However we had the sense of the test inverted; fix this so that the bit reads correctly. To avoid this regressing the behaviour of the user-mode emulator, we must set the DZE bit in the SCTLR for that config so that userspace continues to see DZP as zero (it was getting the correct result by accident previously). Reported-by: Christopher Covington Signed-off-by: Peter Maydell Reviewed-by: Christopher Covington --- target-arm/cpu.c | 4 ++-- target-arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index edfd586..28e2701 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -102,8 +102,8 @@ static void arm_cpu_reset(CPUState *s) env->aarch64 = 1; #if defined(CONFIG_USER_ONLY) env->pstate = PSTATE_MODE_EL0t; - /* Userspace expects access to CTL_EL0 and the cache ops */ - env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; + /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ + env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; /* and to the FP/Neon instructions */ env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); #else diff --git a/target-arm/helper.c b/target-arm/helper.c index 2669e15..904f101 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2018,7 +2018,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) int dzp_bit = 1 << 4; /* DZP indicates whether DC ZVA access is allowed */ - if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) { + if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) { dzp_bit = 0; } return cpu->dcz_blocksize | dzp_bit;