From patchwork Wed Nov 5 23:23:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 40240 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f69.google.com (mail-la0-f69.google.com [209.85.215.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id DDBDF24538 for ; Wed, 5 Nov 2014 23:33:45 +0000 (UTC) Received: by mail-la0-f69.google.com with SMTP id q1sf1079323lam.8 for ; Wed, 05 Nov 2014 15:33:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=vL3csjodyhpk5dEvNFLvr7oJjkf+p54VzT5AWTbJFYw=; b=kFwFl2PxHf39vjeSWSRHmwnCKkLIZoen6Xjknx9rQVjhGbul7SUv3s99Z5T3rvItbw TkY+XpwRQNHI3VvRTTcIgNIJS7tL/l2nGU8HyMfKmJd6LON7XMeb52yvPMS/exqqDyJm Z5ZtRIlPdshtsywzFwZUzefhB6dS+DaLbfGvrXfPbMd6rzKrNucZDtz9mQvW5RCfsV+E iZAXovxbeEWOoiEGiSVfEV+BNpsgPhucpy9G2tlOnZKZM0VlYezvTNw1wg2MamoqVQyC apDZE2eqESkqsql4kHCGDF/jTPoVeC2FXKrLjbWVv37ZSn5NJGhHQwAZmuJkLS7tXbsn vR2Q== X-Gm-Message-State: ALoCoQl4z324Pt0OjomRniBXDbH9wy+Rpa0Evc0EefNka1hoMYw0JRl6UIW2rPJdc0l7zX6dOOpU X-Received: by 10.180.221.7 with SMTP id qa7mr774427wic.6.1415230423185; Wed, 05 Nov 2014 15:33:43 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.26.98 with SMTP id k2ls11624lag.15.gmail; Wed, 05 Nov 2014 15:33:42 -0800 (PST) X-Received: by 10.152.2.41 with SMTP id 9mr523226lar.47.1415230422915; Wed, 05 Nov 2014 15:33:42 -0800 (PST) Received: from mail-lb0-f171.google.com (mail-lb0-f171.google.com. [209.85.217.171]) by mx.google.com with ESMTPS id ri5si8634761lbb.115.2014.11.05.15.33.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:33:42 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) client-ip=209.85.217.171; Received: by mail-lb0-f171.google.com with SMTP id b6so1588418lbj.2 for ; Wed, 05 Nov 2014 15:33:42 -0800 (PST) X-Received: by 10.152.87.100 with SMTP id w4mr552966laz.27.1415230422367; Wed, 05 Nov 2014 15:33:42 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp372182lbc; Wed, 5 Nov 2014 15:33:41 -0800 (PST) X-Received: by 10.140.17.67 with SMTP id 61mr785923qgc.59.1415230420937; Wed, 05 Nov 2014 15:33:40 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q1si6199353qab.95.2014.11.05.15.33.40 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:33:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:49039 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmA56-0004wi-5f for patch@linaro.org; Wed, 05 Nov 2014 18:33:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56406) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vZ-0004Pg-3W for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vU-0004fA-2F for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:49 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:60923) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vT-0004ev-Oo for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:43 -0500 Received: by mail-pa0-f44.google.com with SMTP id bj1so1779484pad.3 for ; Wed, 05 Nov 2014 15:23:43 -0800 (PST) X-Received: by 10.68.232.226 with SMTP id tr2mr314552pbc.89.1415229823105; Wed, 05 Nov 2014 15:23:43 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r4sm4086349pdm.93.2014.11.05.15.23.41 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:23:42 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Wed, 5 Nov 2014 17:23:01 -0600 Message-Id: <1415229793-3278-15-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.44 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v9 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits are used to control whether the CPSR masking bits can be adjusted from non-secure state. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v8 -> v9 - Move cpsr_write mask filtering above mode switch. - Replace conditional checks removed in v8. v7 -> v8 - Fixed incorrect use of env->uncached_cpsr A/I/F to use env->daif instead. - Removed incorrect statement about SPSR to CPSR copies being affected by SCR.AW/FW. - Fix typo in comment. - Simpified cpsr_write logic v3 -> v4 - Fixed up conditions for ignoring CPSR.A/F updates by isolating to v7 and checking for the existence of EL3 and non-existence of EL2. --- target-arm/helper.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 70ba884..1091e0b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3644,6 +3644,8 @@ uint32_t cpsr_read(CPUARMState *env) void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) { + uint32_t changed_daif; + if (mask & CPSR_NZCV) { env->ZF = (~val) & CPSR_Z; env->NF = val; @@ -3666,8 +3668,57 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) env->GE = (val >> 16) & 0xf; } - env->daif &= ~(CPSR_AIF & mask); - env->daif |= val & CPSR_AIF & mask; + /* In a V7 implementation that includes the security extensions but does + * not include Virtualization Extensions the SCR.FW and SCR.AW bits control + * whether non-secure software is allowed to change the CPSR_F and CPSR_A + * bits respectively. + * + * In a V8 implementation, it is permitted for privileged software to + * change the CPSR A/F bits regardless of the SCR.AW/FW bits. + */ + if (!arm_feature(env, ARM_FEATURE_V8) && + arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2) && + !arm_is_secure(env)) { + + changed_daif = (env->daif ^ val) & mask; + + if (changed_daif & CPSR_A) { + /* Check to see if we are allowed to change the masking of async + * abort exceptions from a non-secure state. + */ + if (!(env->cp15.scr_el3 & SCR_AW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_A flag from " + "non-secure world with SCR.AW bit clear\n"); + mask &= ~CPSR_A; + } + } + + if (changed_daif & CPSR_F) { + /* Check to see if we are allowed to change the masking of FIQ + * exceptions from a non-secure state. + */ + if (!(env->cp15.scr_el3 & SCR_FW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_F flag from " + "non-secure world with SCR.FW bit clear\n"); + mask &= ~CPSR_F; + } + + /* Check whether non-maskable FIQ (NMFI) support is enabled. + * If this bit is set software is not allowed to mask + * FIQs, but is allowed to set CPSR_F to 0. + */ + if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && + (val & CPSR_F)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to enable CPSR_F flag " + "(non-maskable FIQ [NMFI] support enabled)\n"); + mask &= ~CPSR_F; + } + } + } if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { if (bad_mode_switch(env, val & CPSR_M)) { @@ -3680,6 +3731,10 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) switch_mode(env, val & CPSR_M); } } + + env->daif &= ~(CPSR_AIF & mask); + env->daif |= val & CPSR_AIF & mask; + mask &= ~CACHED_CPSR_BITS; env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); }