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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id u94si25422870qgu.115.2015.02.25.08.07.24 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 25 Feb 2015 08:07:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:54792 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeUd-0001du-Kc for patch@linaro.org; Wed, 25 Feb 2015 11:07:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeQG-0002ZA-5Q for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YQeQF-0006us-GI for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:52 -0500 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:47158 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeQF-0006uk-BB for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:51 -0500 Received: from localhost ([127.0.0.1] helo=zen.linaroharston) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1YQfOG-0007hX-M5; Wed, 25 Feb 2015 18:04:52 +0100 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 25 Feb 2015 16:02:39 +0000 Message-Id: <1424880159-29348-8-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1424880159-29348-1-git-send-email-alex.bennee@linaro.org> References: <1424880159-29348-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: Peter Maydell , kvm@vger.kernel.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH 6/6] target-arm/cpu.h: document why env->spsr exists X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 I was getting very confused about the duplication of state. Perhaps we should just get rid of env->spsr and use helpers that understand the banking? Signed-off-by: Alex Bennée Reviewed-by: Greg Bellows diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 11845a6..d7fd13f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -155,6 +155,11 @@ typedef struct CPUARMState { This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ uint32_t uncached_cpsr; + /* The spsr is a alias for spsr_elN where N is the current + * exception level. It is provided for here so the TCG msr/mrs + * implementation can access one register. Care needs to be taken + * to ensure the banked_spsr[] is also updated. + */ uint32_t spsr; /* Banked registers. */