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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w58si5220548qtc.98.2016.07.15.06.07.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 15 Jul 2016 06:07:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:60643 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bO2q9-0006uP-VO for patch@linaro.org; Fri, 15 Jul 2016 09:07:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53368) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bO2jr-0008Mw-DB for qemu-devel@nongnu.org; Fri, 15 Jul 2016 09:01:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bO2jp-0003JC-BT for qemu-devel@nongnu.org; Fri, 15 Jul 2016 09:01:06 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46851) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bO2jh-0003HS-TH; Fri, 15 Jul 2016 09:00:58 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3765ED4D76; Fri, 15 Jul 2016 13:00:57 +0000 (UTC) Received: from hawk.localdomain.com (ovpn-204-44.brq.redhat.com [10.40.204.44]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u6FD0gcA018213; Fri, 15 Jul 2016 09:00:54 -0400 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andre.przywara@arm.com, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Fri, 15 Jul 2016 15:00:35 +0200 Message-Id: <1468587641-7300-5-git-send-email-drjones@redhat.com> In-Reply-To: <1468587641-7300-1-git-send-email-drjones@redhat.com> References: <1468587641-7300-1-git-send-email-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Fri, 15 Jul 2016 13:00:57 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH v3 04/10] arm/arm64: add some delay routines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, eric.auger@redhat.com, wei@redhat.com, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow a thread to wait some specified amount of time. Can specify in cycles, usecs, and msecs. Reviewed-by: Alex Bennée Signed-off-by: Andrew Jones --- lib/arm/asm/processor.h | 19 +++++++++++++++++++ lib/arm/processor.c | 15 +++++++++++++++ lib/arm64/asm/processor.h | 19 +++++++++++++++++++ lib/arm64/processor.c | 15 +++++++++++++++ 4 files changed, 68 insertions(+) -- 2.7.4 diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h index d2048f5f5f7e6..afc903ca7d4ab 100644 --- a/lib/arm/asm/processor.h +++ b/lib/arm/asm/processor.h @@ -5,7 +5,9 @@ * * This work is licensed under the terms of the GNU LGPL, version 2. */ +#include #include +#include enum vector { EXCPTN_RST, @@ -51,4 +53,21 @@ extern int mpidr_to_cpu(unsigned long mpidr); extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); extern bool is_user(void); +static inline u64 get_cntvct(void) +{ + u64 vct; + isb(); + asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (vct)); + return vct; +} + +extern void delay(u64 cycles); +extern void udelay(unsigned long usecs); + +static inline void mdelay(unsigned long msecs) +{ + while (msecs--) + udelay(1000); +} + #endif /* _ASMARM_PROCESSOR_H_ */ diff --git a/lib/arm/processor.c b/lib/arm/processor.c index 54fdb87ef0196..c2ee360df6884 100644 --- a/lib/arm/processor.c +++ b/lib/arm/processor.c @@ -9,6 +9,7 @@ #include #include #include +#include static const char *processor_modes[] = { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , @@ -141,3 +142,17 @@ bool is_user(void) { return current_thread_info()->flags & TIF_USER_MODE; } + +void delay(u64 cycles) +{ + u64 start = get_cntvct(); + while ((get_cntvct() - start) < cycles) + cpu_relax(); +} + +void udelay(unsigned long usec) +{ + unsigned int frq; + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); + delay((u64)usec * frq / 1000000); +} diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h index 7e448dc81a6aa..94f7ce35b65c1 100644 --- a/lib/arm64/asm/processor.h +++ b/lib/arm64/asm/processor.h @@ -17,8 +17,10 @@ #define SCTLR_EL1_M (1 << 0) #ifndef __ASSEMBLY__ +#include #include #include +#include enum vector { EL1T_SYNC, @@ -89,5 +91,22 @@ extern int mpidr_to_cpu(unsigned long mpidr); extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); extern bool is_user(void); +static inline u64 get_cntvct(void) +{ + u64 vct; + isb(); + asm volatile("mrs %0, cntvct_el0" : "=r" (vct)); + return vct; +} + +extern void delay(u64 cycles); +extern void udelay(unsigned long usecs); + +static inline void mdelay(unsigned long msecs) +{ + while (msecs--) + udelay(1000); +} + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM64_PROCESSOR_H_ */ diff --git a/lib/arm64/processor.c b/lib/arm64/processor.c index deeab4ec9c8ac..50fa835c6f1e3 100644 --- a/lib/arm64/processor.c +++ b/lib/arm64/processor.c @@ -9,6 +9,7 @@ #include #include #include +#include static const char *vector_names[] = { "el1t_sync", @@ -253,3 +254,17 @@ bool is_user(void) { return current_thread_info()->flags & TIF_USER_MODE; } + +void delay(u64 cycles) +{ + u64 start = get_cntvct(); + while ((get_cntvct() - start) < cycles) + cpu_relax(); +} + +void udelay(unsigned long usec) +{ + unsigned int frq; + asm volatile("mrs %0, cntfrq_el0" : "=r" (frq)); + delay((u64)usec * frq / 1000000); +}