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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id f35si608278qki.181.2016.08.11.08.58.18 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 11 Aug 2016 08:58:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49337 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bXsN8-00056E-Dh for patch@linaro.org; Thu, 11 Aug 2016 11:58:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58791) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bXrwZ-00020v-4u for qemu-devel@nongnu.org; Thu, 11 Aug 2016 11:30:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bXrwW-0007sp-UQ for qemu-devel@nongnu.org; Thu, 11 Aug 2016 11:30:50 -0400 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:36642) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bXrwW-0007sj-KY for qemu-devel@nongnu.org; Thu, 11 Aug 2016 11:30:48 -0400 Received: by mail-wm0-x22d.google.com with SMTP id q128so7382824wma.1 for ; Thu, 11 Aug 2016 08:30:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lsZmppCOHXOyfAOJ880duDidWHotKJX0UOfYnxc6qs0=; b=hFa3ooiJgK+t5V2mbWTYFwjdgjvPt6IPJIE9PEpN0z4Yf+Ld4GeDMjC0XLZAkXh65y m5MGTx3LOI7kkpeDi0q1ODJvgVGE3HhwLRszYxjoeo+fkz1w84PsYs96p0nqYrYHAJH6 LkGfpKyOgSzisHxGY2808aNmpkWGWNQZp4Uy4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lsZmppCOHXOyfAOJ880duDidWHotKJX0UOfYnxc6qs0=; b=X+krXPpEI+OolShUg4wJb3VLYXRfxMscf+vS4Nlj5L+yADgw7/p5hD4VyVA58ARP5t 6wNT7/xwUbghgdvX/cBtq5wPOte0ayQVINNbQgC0QuJpz4+4/JtE/3yDk+XZdZJOZ9Ww 0ntn5PTPKElznoej74q2GX047U5/LKrB3PX91UxWHKL/akYkusEeUGZjy7UaXJhyRtn4 audTWgDzjfYEAApdMPYxglViVL0ls/jrogPOFoOPAuhN0oyTUNA9JpNeh5cIcLNbKvtu iaresJ73Y0TaEPNvujghaR6AjWyY5RdqiGD17s9NyFeUzluJ/q3yPe8YoaHVuqHZZ1eN Mqhw== X-Gm-Message-State: AEkoousPCVuIglfJssvVn9gbU7LYBKpE14A2hZn+nHdxkv9ZU5w3RBLqbfwUD6s6xW7+QVqi X-Received: by 10.28.17.138 with SMTP id 132mr9420289wmr.81.1470929447857; Thu, 11 Aug 2016 08:30:47 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id q4sm3216216wjk.24.2016.08.11.08.30.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Aug 2016 08:30:43 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id A38383E034F; Thu, 11 Aug 2016 16:24:31 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com Date: Thu, 11 Aug 2016 16:24:20 +0100 Message-Id: <1470929064-4092-25-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1470929064-4092-1-git-send-email-alex.bennee@linaro.org> References: <1470929064-4092-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [RFC v4 24/28] cputlb: add assert_cpu_is_self checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, claudio.fontana@huawei.com, Peter Crosthwaite , jan.kiszka@siemens.com, mark.burton@greensocs.com, serge.fdrv@gmail.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , rth@twiddle.net Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For SoftMMU the TLB flushes are an example of a task that can be triggered on one vCPU by another. To deal with this properly we need to use safe work to ensure these changes are done safely. The new assert can be enabled while debugging to catch these cases. Signed-off-by: Alex Bennée --- cputlb.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.7.4 diff --git a/cputlb.c b/cputlb.c index 6f19daa..b6833fe 100644 --- a/cputlb.c +++ b/cputlb.c @@ -59,6 +59,12 @@ } \ } while (0) +#define assert_cpu_is_self(this_cpu) do { \ + if (DEBUG_TLB_GATE) { \ + g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ + } \ + } while (0) + /* statistics */ int tlb_flush_count; @@ -78,6 +84,7 @@ void tlb_flush(CPUState *cpu, int flush_global) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("(%d)\n", flush_global); memset(env->tlb_table, -1, sizeof(env->tlb_table)); @@ -94,6 +101,7 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("start\n"); for (;;) { @@ -138,6 +146,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) int i; int mmu_idx; + assert_cpu_is_self(cpu); tlb_debug("page :" TARGET_FMT_lx "\n", addr); /* Check if we need to flush due to large pages. */ @@ -175,6 +184,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) va_start(argp, addr); + assert_cpu_is_self(cpu); tlb_debug("addr "TARGET_FMT_lx"\n", addr); /* Check if we need to flush due to large pages. */ @@ -263,6 +273,8 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) int mmu_idx; + assert_cpu_is_self(cpu); + env = cpu->env_ptr; for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; @@ -294,6 +306,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) int i; int mmu_idx; + assert_cpu_is_self(cpu); + vaddr &= TARGET_PAGE_MASK; i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { @@ -353,6 +367,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE; int asidx = cpu_asidx_from_attrs(cpu, attrs); + assert_cpu_is_self(cpu); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { tlb_add_large_page(env, vaddr, size);