From patchwork Mon Oct 10 18:11:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Hanson X-Patchwork-Id: 77454 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp37556qge; Mon, 10 Oct 2016 11:13:59 -0700 (PDT) X-Received: by 10.200.36.13 with SMTP id c13mr7413954qtc.26.1476123239038; Mon, 10 Oct 2016 11:13:59 -0700 (PDT) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 8si10025023qtu.127.2016.10.10.11.13.58 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 10 Oct 2016 11:13:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51857 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btf5K-0002er-Id for patch@linaro.org; Mon, 10 Oct 2016 14:13:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49283) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btf3O-0001o5-0r for qemu-devel@nongnu.org; Mon, 10 Oct 2016 14:11:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1btf3J-0003tL-Lu for qemu-devel@nongnu.org; Mon, 10 Oct 2016 14:11:56 -0400 Received: from g4t3427.houston.hpe.com ([15.241.140.73]:7270) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btf3J-0003qt-GG for qemu-devel@nongnu.org; Mon, 10 Oct 2016 14:11:53 -0400 Received: from TomH-Z-Workstation.americas.hpqcorp.net (tomh-z-workstation.americas.hpqcorp.net [16.78.178.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 408954E; Mon, 10 Oct 2016 18:11:49 +0000 (UTC) From: Thomas Hanson To: qemu-devel@nongnu.org Date: Mon, 10 Oct 2016 12:11:16 -0600 Message-Id: <1476123077-35698-4-git-send-email-thomas.hanson@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476123077-35698-1-git-send-email-thomas.hanson@linaro.org> References: <1476123077-35698-1-git-send-email-thomas.hanson@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 15.241.140.73 Subject: [Qemu-devel] [PATCH v2 3/4] target-arm: Comments to mark location of pending work for 56 bit addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: grant.likely@hpe.com, peter.maydell@linaro.org, thomas.hanson@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Certain instructions which can not directly load a tagged address value may trigger a corner case when the address size is 56 bits. This is because incrementing or offsetting from the current PC can cause an arithetic roll-over into the tag bits. Per the ARM ARM spec, these cases should also be addressed by cleaning up the tag field. Signed-off-by: Thomas Hanson --- target-arm/translate-a64.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 1.9.1 diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 14e91fb..a1e5f2c 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1222,6 +1222,9 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { + /*If/when address size is 56 bits, this could overflow into address tag + * byte, and that byte should be fixed per ARM ARM spec. + */ uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; if (insn & (1U << 31)) { @@ -1249,6 +1252,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) sf = extract32(insn, 31, 1); op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ rt = extract32(insn, 0, 5); + /*If/when address size is 56 bits, this could overflow into address tag + * byte, and that byte should be fixed per ARM ARM spec. + */ addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; tcg_cmp = read_cpu_reg(s, rt, sf); @@ -1277,6 +1283,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ + /*If/when address size is 56 bits, this could overflow into address tag + * byte, and that byte should be fixed per ARM ARM spec. + */ addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; rt = extract32(insn, 0, 5); @@ -1306,6 +1315,9 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } + /*If/when address size is 56 bits, this could overflow into address tag + * byte, and that byte should be fixed per ARM ARM spec. + */ addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; cond = extract32(insn, 0, 4);