From patchwork Mon Oct 24 17:25:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 79060 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp2729897qge; Mon, 24 Oct 2016 11:42:52 -0700 (PDT) X-Received: by 10.176.3.81 with SMTP id 75mr10332388uat.37.1477334572602; Mon, 24 Oct 2016 11:42:52 -0700 (PDT) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id d88si5917454uad.212.2016.10.24.11.42.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 24 Oct 2016 11:42:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48869 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bykCx-0007GW-Ec for patch@linaro.org; Mon, 24 Oct 2016 14:42:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1byj0O-0006Wn-Pm for qemu-devel@nongnu.org; Mon, 24 Oct 2016 13:25:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1byj0M-0007Wr-Km for qemu-devel@nongnu.org; Mon, 24 Oct 2016 13:25:48 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47425) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1byj0M-0007UC-Ch for qemu-devel@nongnu.org; Mon, 24 Oct 2016 13:25:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1byj07-0002JY-QB for qemu-devel@nongnu.org; Mon, 24 Oct 2016 18:25:31 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 24 Oct 2016 18:25:02 +0100 Message-Id: <1477329928-26414-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477329928-26414-1-git-send-email-peter.maydell@linaro.org> References: <1477329928-26414-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/32] target-arm: Make page size a runtime setting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than defining TARGET_PAGE_BITS to always be 10, switch to using a value picked at runtime. This allows us to use 4K pages for modern ARM CPUs (and in particular all 64-bit CPUs) without having to drop support for the old ARMv5 CPUs which had 1K pages. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/cpu.c | 24 ++++++++++++++++++++++++ target-arm/cpu.h | 9 +++++---- 2 files changed, 29 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1b9540e..c94a324 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -576,6 +576,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) ARMCPU *cpu = ARM_CPU(dev); ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); CPUARMState *env = &cpu->env; + int pagebits; /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { @@ -631,6 +632,29 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) set_feature(env, ARM_FEATURE_THUMB_DSP); } + if (arm_feature(env, ARM_FEATURE_V7) && + !arm_feature(env, ARM_FEATURE_M) && + !arm_feature(env, ARM_FEATURE_MPU)) { + /* v7VMSA drops support for the old ARMv5 tiny pages, so we + * can use 4K pages. + */ + pagebits = 12; + } else { + /* For CPUs which might have tiny 1K pages, or which have an + * MPU and might have small region sizes, stick with 1K pages. + */ + pagebits = 10; + } + if (!set_preferred_target_page_bits(pagebits)) { + /* This can only ever happen for hotplugging a CPU, or if + * the board code incorrectly creates a CPU which it has + * promised via minimum_page_size that it will not. + */ + error_setg(errp, "This CPU requires a smaller page size than the " + "system is using"); + return; + } + if (cpu->reset_hivecs) { cpu->reset_sctlr |= (1 << 13); } diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2218c00..6695390 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1766,10 +1766,11 @@ bool write_cpustate_to_list(ARMCPU *cpu); #if defined(CONFIG_USER_ONLY) #define TARGET_PAGE_BITS 12 #else -/* The ARM MMU allows 1k pages. */ -/* ??? Linux doesn't actually use these, and they're deprecated in recent - architecture revisions. Maybe a configure option to disable them. */ -#define TARGET_PAGE_BITS 10 +/* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 + * have to support 1K tiny pages. + */ +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 10 #endif #if defined(TARGET_AARCH64)