From patchwork Sun Jun 23 17:04:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 167534 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3232233ilk; Sun, 23 Jun 2019 10:14:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqzN48w6kae9WdghcJHKHkPlNzDMIj+yfw0v25pYIAX8VuEPShECP4IsKr4W7VcuuYl+rSH+ X-Received: by 2002:a50:fb0a:: with SMTP id d10mr77486910edq.124.1561310094730; Sun, 23 Jun 2019 10:14:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561310094; cv=none; d=google.com; s=arc-20160816; b=05tIdhTNmbLWytFgn9Pdo/Yo1/h6GZJGLXM9D5BvB29LRYPBRcHG4EQtyXCcTNp4nm ubmY95zLaQJ2vXWdzw2ivkP/ZAFrfoomxHdFCI2y2NjHXlP14AHIEo0NlGvUfnVI45/X eWQSWQ6i2SFSfaFJFIOe0Am1FaZ2HE+46IdtfwZ0eZMa5hINfARN0fMpSbTYza4db4ZL VTDO0gyVN8epJBnWPckLFtAVh/FtIxeHB7BKWKrDjXK4ecAnFCFVxZjrgycBtW7qbplj KLqRFiIwpJZ4YYjHAZk6jsb4sleP9Df/lHxJQQzI4yAjX+Q+m8MkKjCD4gwmlF6fXiDk weng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from; bh=7FK1OnZafF4kAvRk+97BVR+QT30/V+lZnmVRl9oe/2k=; b=Mbm59u2slJW9ZJjl/Xj97kJ8ZmDgLx54nEGh3LOOjFSW97b9mWXOvk9FZO7OiFD9Ru wtbQ7KaolUIYpIB11ZBkUIPJ3ZTQNl1YEolbF2xyljAeYWSHpus3wWmn9UM4QX3GE67/ XxovFJ1l/fiuyzYoWUzaPz/gR7Pa0vj1LRhFs64xrYER+D7v1gqGZjDedAbMq66/o6F0 T0Z43SRUj3j4YqJst9LGXwUQDGarlzkldCKibAu2HZu2SrQYqOJoL7TNv9/Q6yal3/5d xc8uyiqMPvVT19D7EufXsUpLFKWe1/E/qaCrjtET7Zz1sXlkRkFB+TfXPWWT1xaNHW/M nwxQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o25si591338eju.237.2019.06.23.10.14.54 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Jun 2019 10:14:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:45848 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf64r-0000uK-NJ for patch@linaro.org; Sun, 23 Jun 2019 13:14:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34205) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf5wO-0001fq-Rq for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hf5wM-0004Lr-Q2 for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:08 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41130 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hf5wM-0004JL-Cp for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:06 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id AD57A1A1DD6; Sun, 23 Jun 2019 19:05:45 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 763A81A1DBE; Sun, 23 Jun 2019 19:05:45 +0200 (CEST) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sun, 23 Jun 2019 19:04:44 +0200 Message-Id: <1561309489-16146-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 11/16] tcg/ppc: Support vector shift by immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, "David Gibson --cc=amarkovic @ wavecomp . com" , Mark Cave-Ayland , Aleksandar Markovic , hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson For Altivec, this is done via vector shift by vector, and loading the immediate into a register. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 368c250..766706f 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -152,7 +152,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 03a48c9..3eb18cb 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -517,6 +517,16 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) +#define VSLB VX4(260) +#define VSLH VX4(324) +#define VSLW VX4(388) +#define VSRB VX4(516) +#define VSRH VX4(580) +#define VSRW VX4(644) +#define VSRAB VX4(772) +#define VSRAH VX4(836) +#define VSRAW VX4(900) + #define VAND VX4(1028) #define VANDC VX4(1092) #define VNOR VX4(1284) @@ -2861,8 +2871,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return vece <= MO_32; case INDEX_op_cmp_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: return vece <= MO_32 ? -1 : 0; default: return 0; @@ -2970,7 +2986,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 }, smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 }, umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 }, - smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 }; + smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 }, + shlv_op[4] = { VSLB, VSLH, VSLW, 0 }, + shrv_op[4] = { VSRB, VSRH, VSRW, 0 }, + sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 }; TCGType type = vecl + TCG_TYPE_V64; TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; @@ -3017,6 +3036,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_umax_vec: insn = umax_op[vece]; break; + case INDEX_op_shlv_vec: + insn = shlv_op[vece]; + break; + case INDEX_op_shrv_vec: + insn = shrv_op[vece]; + break; + case INDEX_op_sarv_vec: + insn = sarv_op[vece]; + break; case INDEX_op_and_vec: insn = VAND; break; @@ -3061,6 +3089,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); } +static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGArg imm, TCGOpcode opci) +{ + TCGv_vec t1 = tcg_temp_new_vec(type); + + /* Splat w/bytes for xxspltib. */ + tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); + vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); +} + static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGCond cond) { @@ -3112,14 +3152,25 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, { va_list va; TCGv_vec v0, v1, v2; + TCGArg a2; va_start(va, a0); v0 = temp_tcgv_vec(arg_temp(a0)); v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 = va_arg(va, TCGArg); switch (opc) { + case INDEX_op_shli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); + break; + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); + break; + case INDEX_op_sari_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); + break; case INDEX_op_cmp_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; default: @@ -3320,6 +3371,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: