From patchwork Sun Jun 23 17:04:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 167540 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3242526ilk; Sun, 23 Jun 2019 10:27:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqwfDpEZlBPscv0CLFFX/wpmSdTf1x+AR6wLuIAw4sdbAImqToSbGirJPTMGlphKfWKC/cCa X-Received: by 2002:a50:9157:: with SMTP id f23mr48598649eda.79.1561310836471; Sun, 23 Jun 2019 10:27:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561310836; cv=none; d=google.com; s=arc-20160816; b=URuyrmEl/m75Xk7WmzCpgoRMoN3b+5EHpBK0jFfE6/EfWsVTWzDJIBbi9s9E2Vgu/e HCE+wbhWBpJWMxugAQSIYQvlXbEWDLjdVNZ31f7qtpw67vlrxnkhdc2XiAhwq77b013p IQP7j5PgHu4msDG/nEgABVcwSrh0ts2qqrZ1+SUEiyPPe1BnycdSGRNt/th3VJFDDbFc Q5AJEjc3JgIbp7cLv6sXNx3H5EPged1L2r5/fyHAINDMte+cy49tqh7ZEUsv9xLZENOG rbxSOjQJ/klKXjMYLAzJSdqjA6Lw631onCqDNMbY8+ImUvgJioke76ZeT/+L98ZFes9b YW8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from; bh=jpFFSdL7+4ylXXlvRvPGyvG2O9sRrELGNtpjQtGUE04=; b=r8SbVVRuOl4iUAvbuqbpQAeQJV/JiN64vCTxoSmeGgnr4fTSeQ7m2rjmjqlJl8YO1x zc+lfjC1R2J6rhOh1Y7coItz2wY+diOfpgRgbpXx7an1/TToW2F73zgasO5yAIm9FC2f aZFxcU6L/9MianpdHozqesVB8cG+vVnL9vLrFl47yGDRH2+cNA+SMcAoJ3zDFxoQNdjU Rew1p2I/QmZYEvotFe9woDi2Zv+YFfahsJ3bwbkIDYn+1ReD36PAfNxcQYBYI/T2KnXV jmQuQxryqnnr6d/Ey/xwl102ld1aY43LTVc/yMYV9uSdk9EgiqZkKRK/R7/sGAUBs+Xv nhzQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p6si3222923ejg.75.2019.06.23.10.27.16 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Jun 2019 10:27:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:45948 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf6Gp-0003Mg-GP for patch@linaro.org; Sun, 23 Jun 2019 13:27:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34290) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf5wg-0001kq-Vb for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hf5wc-0004jb-3b for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:25 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39474 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hf5wV-0003MV-Am for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:17 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 59A6C1A1D2D; Sun, 23 Jun 2019 19:05:11 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3D9F61A1D2A; Sun, 23 Jun 2019 19:05:11 +0200 (CEST) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sun, 23 Jun 2019 19:04:35 +0200 Message-Id: <1561309489-16146-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, "David Gibson --cc=amarkovic @ wavecomp . com" , Mark Cave-Ayland , Aleksandar Markovic , hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Detect during initialization if the emulated CPU supports Altivec, and store the result in the flag have_isa_altivec. The definition of Altivec SIMD instructions set evolved over time. Different generations of Altivec will be distinguished by other flags in TCG, and they are currently have_isa_2_06 and have_isa_3_00. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.h | 25 +++++++++++++++++++++++++ tcg/ppc/tcg-target.inc.c | 8 ++++++++ 2 files changed, 33 insertions(+) -- 2.7.4 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 690fa74..f6283f4 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -58,6 +58,7 @@ typedef enum { TCG_AREG0 = TCG_REG_R27 } TCGReg; +extern bool have_isa_altivec; extern bool have_isa_2_06; extern bool have_isa_3_00; @@ -135,6 +136,30 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_mulsh_i64 1 #endif +/* + * While technically Altivec could support V64, it has no 64-bit store + * instruction and substituting two 32-bit stores makes the generated + * code quite large. + */ +#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_v128 have_isa_altivec +#define TCG_TARGET_HAS_v256 0 + +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_cmp_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 + void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 8e1bba7..26892de 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -64,6 +64,7 @@ static tcg_insn_unit *tb_ret_addr; +bool have_isa_altivec; bool have_isa_2_06; bool have_isa_3_00; @@ -2781,6 +2782,9 @@ static void tcg_target_init(TCGContext *s) unsigned long hwcap = qemu_getauxval(AT_HWCAP); unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); + if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { + have_isa_altivec = true; + } if (hwcap & PPC_FEATURE_ARCH_2_06) { have_isa_2_06 = true; } @@ -2792,6 +2796,10 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; + if (have_isa_altivec) { + tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; + } tcg_target_call_clobber_regs = 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);