From patchwork Mon Sep 28 12:36:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 272601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD071C2D0A8 for ; Mon, 28 Sep 2020 13:08:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63D8120739 for ; Mon, 28 Sep 2020 13:08:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="mPBxr5Wn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 63D8120739 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:42144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kMstA-0001Oe-Fm for qemu-devel@archiver.kernel.org; Mon, 28 Sep 2020 09:08:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49932) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kMsP6-0004Kh-0V for qemu-devel@nongnu.org; Mon, 28 Sep 2020 08:37:16 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:46899) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kMsP3-0005eW-Ec for qemu-devel@nongnu.org; Mon, 28 Sep 2020 08:37:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1601296633; x=1632832633; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Xr0dSzItmvM5bSRls/4sIMpBdyRC7yrAqq7p4Jv+3Z4=; b=mPBxr5WnoxXd2icl6Cl0MRyBCRJVxF3xwnF4o9lU0jX560I5IFiAcLSR hnivyVYEDXtpwbeJOXHwW7SpGUWXC3FyGDh86SVAyKIKCmv9XNYEI+FBW jQgHHA6qQshfzyJ25SVTo+WuNTWnytKHLhs4hIK2j7XK+7/nMcyaNTrg1 o=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 28 Sep 2020 05:36:54 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 28 Sep 2020 05:36:54 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 67DDF1184; Mon, 28 Sep 2020 07:36:54 -0500 (CDT) From: Taylor Simpson To: tsimpson@quicinc.com Subject: [RFC PATCH v4 25/29] Hexagon (target/hexagon) TCG for instructions with multiple definitions Date: Mon, 28 Sep 2020 07:36:44 -0500 Message-Id: <1601296608-29390-26-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601296608-29390-1-git-send-email-tsimpson@quicinc.com> References: <1601296608-29390-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/28 08:36:52 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.199, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:All patches CC here" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Helpers won't work if there are multiple definitions, so we override these instructions using #define fGEN_TCG_. Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 198 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 target/hexagon/gen_tcg.h diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h new file mode 100644 index 0000000..35568d1 --- /dev/null +++ b/target/hexagon/gen_tcg.h @@ -0,0 +1,198 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_GEN_TCG_H +#define HEXAGON_GEN_TCG_H + +/* + * Here is a primer to understand the tag names for load/store instructions + * + * Data types + * b signed byte r0 = memb(r2+#0) + * ub unsigned byte r0 = memub(r2+#0) + * h signed half word (16 bits) r0 = memh(r2+#0) + * uh unsigned half word r0 = memuh(r2+#0) + * i integer (32 bits) r0 = memw(r2+#0) + * d double word (64 bits) r1:0 = memd(r2+#0) + * + * Addressing modes + * _io indirect with offset r0 = memw(r1+#4) + * _ur absolute with register offset r0 = memw(r1<<#4+##variable) + * _rr indirect with register offset r0 = memw(r1+r4<<#2) + * gp global pointer relative r0 = memw(gp+#200) + * _sp stack pointer relative r0 = memw(r29+#12) + * _ap absolute set r0 = memw(r1=##variable) + * _pr post increment register r0 = memw(r1++m1) + * _pi post increment immediate r0 = memb(r1++#1) + */ + +/* Macros for complex addressing modes */ +#define GET_EA_ap \ + do { \ + fEA_IMM(UiV); \ + tcg_gen_movi_tl(ReV, UiV); \ + } while (0) +#define GET_EA_pr \ + do { \ + fEA_REG(RxV); \ + fPM_M(RxV, MuV); \ + } while (0) +#define GET_EA_pi \ + do { \ + fEA_REG(RxV); \ + fPM_I(RxV, siV); \ + } while (0) + + +/* Instructions with multiple definitions */ +#define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \ + do { \ + fMUST_IMMEXT(UiV); \ + fEA_IMM(UiV); \ + fLOAD(1, SIZE, SIGN, EA, RES); \ + tcg_gen_movi_tl(ReV, UiV); \ + } while (0) + +#define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 1, u) +#define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 1, s) +#define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 2, u) +#define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 2, s) +#define fGEN_TCG_L4_loadri_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 4, u) +#define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RddV, 8, u) + +#define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE; +#define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE; +#define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE + +/* + * Predicated loads + * Here is a primer to understand the tag names + * + * Predicate used + * t true "old" value if (p0) r0 = memb(r2+#0) + * f false "old" value if (!p0) r0 = memb(r2+#0) + * tnew true "new" value if (p0.new) r0 = memb(r2+#0) + * fnew false "new" value if (!p0.new) r0 = memb(r2+#0) + */ +#define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \ + do { \ + TCGv LSB = tcg_temp_local_new(); \ + TCGLabel *label = gen_new_label(); \ + GET_EA; \ + PRED; \ + PRED_LOAD_CANCEL(LSB, EA); \ + tcg_gen_movi_tl(RdV, 0); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ + fLOAD(1, SIZE, SIGN, EA, RdV); \ + gen_set_label(label); \ + tcg_temp_free(LSB); \ + } while (0) + +#define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u) +#define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u) +#define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u) +#define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u) +#define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s) +#define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s) +#define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s) +#define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \ + fLSBNEWNOT(PtN), 1, s) + +#define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u) +#define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u) +#define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u) +#define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u) +#define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s) +#define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s) +#define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s) +#define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s) + +#define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u) +#define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u) +#define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u) +#define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u) + +/* Predicated loads into a register pair */ +#define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \ + do { \ + TCGv LSB = tcg_temp_local_new(); \ + TCGLabel *label = gen_new_label(); \ + GET_EA; \ + PRED; \ + PRED_LOAD_CANCEL(LSB, EA); \ + tcg_gen_movi_i64(RddV, 0); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ + fLOAD(1, 8, u, EA, RddV); \ + gen_set_label(label); \ + tcg_temp_free(LSB); \ + } while (0) + +#define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV)) +#define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV)) +#define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN)) +#define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN)) + +/* load-locked and store-locked */ +#define fGEN_TCG_L2_loadw_locked(SHORTCODE) \ + SHORTCODE +#define fGEN_TCG_L4_loadd_locked(SHORTCODE) \ + SHORTCODE +#define fGEN_TCG_S2_storew_locked(SHORTCODE) \ + do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) +#define fGEN_TCG_S4_stored_locked(SHORTCODE) \ + do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) + +#endif