From patchwork Fri Oct 30 00:08:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98499C2D0A3 for ; Fri, 30 Oct 2020 00:59:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5D662071A for ; Fri, 30 Oct 2020 00:59:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="xRjXtwNp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E5D662071A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kYIlb-00023z-RW for qemu-devel@archiver.kernel.org; Thu, 29 Oct 2020 20:59:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kYHys-0004Bo-9w for qemu-devel@nongnu.org; Thu, 29 Oct 2020 20:09:22 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:39660) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kYHyp-0005Qi-5q for qemu-devel@nongnu.org; Thu, 29 Oct 2020 20:09:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1604016559; x=1635552559; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MP0p+d0tCPd8RO+KWYmjChAvFvfuCSZjYWt38Th6n6c=; b=xRjXtwNpRGn7znmd8sLjS8MdP1QS1puOEQbR+k5RTftLnHVhpvh0gdi8 Dla9izDo8DI2u2kdAYAvkluZwFq6NpTggLpOIobCQj4h3qo3KEPVk6nyo qRZltq+lV7qRa6C5dIX+PZeiU2NxSPopKOyZY1+2q+scjHrb2bKaUxvEK s=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 29 Oct 2020 17:08:47 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 29 Oct 2020 17:08:46 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 7979A4118; Thu, 29 Oct 2020 19:08:46 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 28/33] Hexagon (target/hexagon) TCG for floating point instructions Date: Thu, 29 Oct 2020 19:08:34 -0500 Message-Id: <1604016519-28065-29-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The imported code uses host floating point. We override them to use qemu softfloat Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 121 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 35568d1..d605b1e 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -195,4 +195,125 @@ #define fGEN_TCG_S4_stored_locked(SHORTCODE) \ do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) +/* Floating point */ +#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ + gen_helper_conv_sf2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \ + gen_helper_conv_df2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \ + gen_helper_conv_uw2sf(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \ + gen_helper_conv_uw2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \ + gen_helper_conv_w2sf(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \ + gen_helper_conv_w2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \ + gen_helper_conv_ud2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \ + gen_helper_conv_ud2df(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \ + gen_helper_conv_d2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \ + gen_helper_conv_d2df(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \ + gen_helper_conv_sf2uw(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \ + gen_helper_conv_sf2w(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \ + gen_helper_conv_sf2ud(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \ + gen_helper_conv_sf2d(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \ + gen_helper_conv_df2uw(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \ + gen_helper_conv_df2w(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \ + gen_helper_conv_df2ud(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \ + gen_helper_conv_df2d(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \ + gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \ + gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \ + gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \ + gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \ + gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \ + gen_helper_conv_df2w_chop(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \ + gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \ + gen_helper_conv_df2d_chop(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_sfadd(SHORTCODE) \ + gen_helper_sfadd(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfsub(SHORTCODE) \ + gen_helper_sfsub(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ + gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ + gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \ + gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \ + gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfmax(SHORTCODE) \ + gen_helper_sfmax(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfmin(SHORTCODE) \ + gen_helper_sfmin(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfclass(SHORTCODE) \ + do { \ + TCGv imm = tcg_const_tl(uiV); \ + gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ + tcg_temp_free(imm); \ + } while (0) +#define fGEN_TCG_F2_sffixupn(SHORTCODE) \ + gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffixupd(SHORTCODE) \ + gen_helper_sffixupd(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffixupr(SHORTCODE) \ + gen_helper_sffixupr(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_dfadd(SHORTCODE) \ + gen_helper_dfadd(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfsub(SHORTCODE) \ + gen_helper_dfsub(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmax(SHORTCODE) \ + gen_helper_dfmax(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmin(SHORTCODE) \ + gen_helper_dfmin(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \ + gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \ + gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \ + gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \ + gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfclass(SHORTCODE) \ + do { \ + TCGv imm = tcg_const_tl(uiV); \ + gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ + tcg_temp_free(imm); \ + } while (0) +#define fGEN_TCG_F2_sfmpy(SHORTCODE) \ + gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffma(SHORTCODE) \ + gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \ + gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV) +#define fGEN_TCG_F2_sffms(SHORTCODE) \ + gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \ + gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \ + gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV) + +#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \ + gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \ + gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV) + #endif