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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id e127si2962778ywc.42.2016.10.27.08.51.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 27 Oct 2016 08:51:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42428 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzmy5-000408-GX for patch@linaro.org; Thu, 27 Oct 2016 11:51:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzmTN-0003io-UI for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:20:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzmTM-0004Vk-CK for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:20:05 -0400 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:38422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bzmTM-0004UL-09 for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:20:04 -0400 Received: by mail-wm0-x22d.google.com with SMTP id n67so51140641wme.1 for ; Thu, 27 Oct 2016 08:20:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RJhWWNaHXuQnQ5+Q+vbZHIpOzJMAu4JWQCMl4azrkdA=; b=ioy+bk7U9NHCvd1w8UgF/P7oSUBEEdXdaYUgNtINw4888NcpN8WkXoAqjmaloQ9VlK yWefB0wqMekHNFmMiH1FgejshVNUdN8MNwW5lCf6Ma9oG+dMaovcCuPa7zWINXu7Jl/v 3HJBZ7Uwnslk4hK5cPcAc70UPzbprJAJKpJ5E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RJhWWNaHXuQnQ5+Q+vbZHIpOzJMAu4JWQCMl4azrkdA=; b=KcylgF4fnQQpx0CiIISICG7nuJlhMfTKFi949x1IPZG217ECu4xCW21TSU7ditGP2M 0kfyVa4GvvHgZlmQtlMkapiq5pSvz+i7phXE3Gd6FQNyLDryykL62FuGTkVZzWnYYRdp R/do/JucX+xsQcFtEQHro9iyKr0fK5XonhLEFfKnlmjye7/JZGvlq0BuDYS7yteIdmt9 JDQoi7YZ6dHM8QmWIQrzGzq4MSiJnLr6TiEHIMqJri9q9a6bzfWHAY7RR6jjlgfIrl8a RKFl/o6Le71USk0uDRtMnZeeNnMJ66M6XLgG91RaIL4BFJra3Q9HH3jDyHlmpdrCplnX hTYQ== X-Gm-Message-State: ABUngveBlllbJ/PEZg+pYthcz7V1w3Vga6wvr7dsJa4rbZVCkDtSNKa0MU6vNTUcmYcvk50T X-Received: by 10.28.6.198 with SMTP id 189mr8858922wmg.16.1477581602832; Thu, 27 Oct 2016 08:20:02 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id io3sm9034114wjb.24.2016.10.27.08.19.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Oct 2016 08:19:59 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 9380A3E03D7; Thu, 27 Oct 2016 16:11:00 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: pbonzini@redhat.com Date: Thu, 27 Oct 2016 16:10:16 +0100 Message-Id: <20161027151030.20863-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161027151030.20863-1-alex.bennee@linaro.org> References: <20161027151030.20863-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [PATCH v5 19/33] tcg: move locking for tb_invalidate_phys_page_range up X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, nikunj@linux.vnet.ibm.com, Peter Crosthwaite , jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, serge.fdrv@gmail.com, bobby.prani@gmail.com, rth@twiddle.net, =?UTF-8?q?Alex=20Benn=C3=A9e?= , fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the linux-user case all things that involve ''l1_map' and PageDesc tweaks are protected by the memory lock (mmpa_lock). For SoftMMU mode we previously relied on single threaded behaviour, with MTTCG we now use the tb_lock(). As a result we need to do a little re-factoring and push the taking of this lock up the call tree. This requires a slightly different entry for the SoftMMU and user-mode cases from tb_invalidate_phys_range. This also means user-mode breakpoint insertion needs to take two locks but it hadn't taken any previously so this is an improvement. Signed-off-by: Alex Bennée --- exec.c | 16 ++++++++++++++++ translate-all.c | 37 +++++++++++++++++++++++++++++-------- 2 files changed, 45 insertions(+), 8 deletions(-) -- 2.10.1 diff --git a/exec.c b/exec.c index 8db5545..738e8ba 100644 --- a/exec.c +++ b/exec.c @@ -651,7 +651,11 @@ void cpu_exec_init(CPUState *cpu, Error **errp) #if defined(CONFIG_USER_ONLY) static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) { + mmap_lock(); + tb_lock(); tb_invalidate_phys_page_range(pc, pc + 1, 0); + tb_unlock(); + mmap_unlock(); } #else static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) @@ -660,6 +664,7 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); int asidx = cpu_asidx_from_attrs(cpu, attrs); if (phys != -1) { + /* Locks grabbed by tb_invalidate_phys_addr */ tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, phys | (pc & ~TARGET_PAGE_MASK)); } @@ -1947,7 +1952,11 @@ ram_addr_t qemu_ram_addr_from_host(void *ptr) static void notdirty_mem_write(void *opaque, hwaddr ram_addr, uint64_t val, unsigned size) { + bool locked = false; + if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { + locked = true; + tb_lock(); tb_invalidate_phys_page_fast(ram_addr, size); } switch (size) { @@ -1963,6 +1972,11 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr, default: abort(); } + + if (locked) { + tb_unlock(); + } + /* Set both VGA and migration bits for simplicity and to remove * the notdirty callback faster. */ @@ -2443,7 +2457,9 @@ static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); } if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { + tb_lock(); tb_invalidate_phys_range(addr, addr + length); + tb_unlock(); dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); } cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); diff --git a/translate-all.c b/translate-all.c index 23a2170..2dd240a 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1383,12 +1383,11 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * access: the virtual CPU will exit the current TB if code is modified inside * this TB. * - * Called with mmap_lock held for user-mode emulation + * Called with mmap_lock held for user-mode emulation, grabs tb_lock + * Called with tb_lock held for system-mode emulation */ -void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) +static void tb_invalidate_phys_range_1(tb_page_addr_t start, tb_page_addr_t end) { - assert_memory_lock(); - while (start < end) { tb_invalidate_phys_page_range(start, end, 0); start &= TARGET_PAGE_MASK; @@ -1396,6 +1395,21 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) } } +#ifdef CONFIG_SOFTMMU +void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) +{ + assert_tb_lock(); + tb_invalidate_phys_range_1(start, end); +} +#else +void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) +{ + assert_memory_lock(); + tb_lock(); + tb_invalidate_phys_range_1(start, end); + tb_unlock(); +} +#endif /* * Invalidate all TBs which intersect with the target physical address range * [start;end[. NOTE: start and end must refer to the *same* physical page. @@ -1403,7 +1417,8 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) * access: the virtual CPU will exit the current TB if code is modified inside * this TB. * - * Called with mmap_lock held for user-mode emulation + * Called with tb_lock/mmap_lock held for user-mode emulation + * Called with tb_lock held for system-mode emulation */ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, int is_cpu_write_access) @@ -1426,6 +1441,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, #endif /* TARGET_HAS_PRECISE_SMC */ assert_memory_lock(); + assert_tb_lock(); p = page_find(start >> TARGET_PAGE_BITS); if (!p) { @@ -1440,7 +1456,6 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, /* we remove all the TBs in the range [start, end[ */ /* XXX: see if in some cases it could be faster to invalidate all the code */ - tb_lock(); tb = p->first_tb; while (tb != NULL) { n = (uintptr_t)tb & 3; @@ -1500,12 +1515,12 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, cpu_loop_exit_noexc(cpu); } #endif - tb_unlock(); } #ifdef CONFIG_SOFTMMU /* len must be <= 8 and start must be a multiple of len. - * Called via softmmu_template.h, with iothread mutex not held. + * Called via softmmu_template.h when code areas are written to with + * tb_lock held. */ void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) { @@ -1520,6 +1535,8 @@ void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) (intptr_t)cpu_single_env->segs[R_CS].base); } #endif + assert_memory_lock(); + p = page_find(start >> TARGET_PAGE_BITS); if (!p) { return; @@ -1567,6 +1584,8 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc) uint32_t current_flags = 0; #endif + assert_memory_lock(); + addr &= TARGET_PAGE_MASK; p = page_find(addr >> TARGET_PAGE_BITS); if (!p) { @@ -1670,7 +1689,9 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) return; } ram_addr = memory_region_get_ram_addr(mr) + addr; + tb_lock(); tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); + tb_unlock(); rcu_read_unlock(); } #endif /* !defined(CONFIG_USER_ONLY) */