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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id m28si3626587uab.93.2016.10.27.09.00.21 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 27 Oct 2016 09:00:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzn6L-0002gz-1Q for patch@linaro.org; Thu, 27 Oct 2016 12:00:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45443) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzmTL-0003ha-AK for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:20:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzmTF-0004OU-S6 for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:20:03 -0400 Received: from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e]:34823) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bzmTF-0004Nl-Kn for qemu-devel@nongnu.org; Thu, 27 Oct 2016 11:19:57 -0400 Received: by mail-wm0-x22e.google.com with SMTP id e69so41512350wmg.0 for ; Thu, 27 Oct 2016 08:19:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P9CWnlGfiA4lMSOYiPrKXW9oO7KFD9wFmUGR2+u3dTY=; b=cUZiwpAIAb8YOgFeIxEag9WYDJu9SPr8y6P61N6CAgJz55m61uILK9H17lizz1neyb w5IG0w6TP6UKbykYSrw7Nv6vPH+0bNNUPsdJZaeS9T7GFdOja3VY//AUl9rBgfU8qHGR zHth/pXYOI5ZWTtpLdZ4+SHilcwM01r+Rx924= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P9CWnlGfiA4lMSOYiPrKXW9oO7KFD9wFmUGR2+u3dTY=; b=EGqwetlM85OjhheO5kUwKioYpgpfy0wsWq1M8UNHsq3o0NieI0wkYNhzJSgS0dasbU 4JM6L5z8zsUZ9/gTyXxlkLpk4+/a87g8atlehJKb8rIFYpEpn/KUdPBSlPnlvDyXBXZg r4g4Jhh8meXnbKqizyRZCsxM58btnGi2hcRJ7jL74YONdxz2UhLHzxOflEwFHkQK4BTy D7ahc+oBR/OTLI128lB2g4EFFUCjIN1aVk4ycfP53TvJGa8JCLzjtsVOQd8vTPnm7xdY WwtgelOo3awbFfnfgbVqi6KdizqQ1td+/+e9DZwBRW2NN4aAKkn6Kr0kKMh605cx63fe zRhQ== X-Gm-Message-State: ABUngvflQezmiCWlxGyUKEsDEth03ew5ABIS9dPx8bNSfIspJ1suq0iQ7Be1H7G5O/pEgZPt X-Received: by 10.28.50.66 with SMTP id y63mr9083412wmy.44.1477581596389; Thu, 27 Oct 2016 08:19:56 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id ya1sm9036453wjb.23.2016.10.27.08.19.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Oct 2016 08:19:55 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 85FFB3E04D2; Thu, 27 Oct 2016 16:11:01 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: pbonzini@redhat.com Date: Thu, 27 Oct 2016 16:10:28 +0100 Message-Id: <20161027151030.20863-32-alex.bennee@linaro.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161027151030.20863-1-alex.bennee@linaro.org> References: <20161027151030.20863-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22e Subject: [Qemu-devel] [PATCH v5 31/33] target-arm: ensure BQL taken for ARM_CP_IO register access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, nikunj@linux.vnet.ibm.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, "open list:ARM cores" , serge.fdrv@gmail.com, bobby.prani@gmail.com, rth@twiddle.net, =?UTF-8?q?Alex=20Benn=C3=A9e?= , fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most ARMCPRegInfo structures just allow updating of the CPU field. However some have more complex operations that *may* be have cross vCPU effects therefor need to be serialised. The most obvious examples at the moment are things that affect the GICv3 IRQ controller. To avoid applying this requirement to all registers with custom access functions we check for if the type is marked ARM_CP_IO. By default all MMIO access to devices already takes the BQL to serialise hardware emulation. Signed-off-by: Alex Bennée --- hw/intc/arm_gicv3_cpuif.c | 3 +++ target-arm/op_helper.c | 39 +++++++++++++++++++++++++++++++++++---- 2 files changed, 38 insertions(+), 4 deletions(-) -- 2.10.1 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index bca30c4..8ea4b5b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -13,6 +13,7 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "trace.h" #include "gicv3_internal.h" #include "cpu.h" @@ -128,6 +129,8 @@ void gicv3_cpuif_update(GICv3CPUState *cs) ARMCPU *cpu = ARM_CPU(cs->cpu); CPUARMState *env = &cpu->env; + g_assert(qemu_mutex_iothread_locked()); + trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq, cs->hppi.grp, cs->hppi.prio); diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index cd94216..4f0c754 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -17,6 +17,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "internals.h" @@ -734,28 +735,58 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value) { const ARMCPRegInfo *ri = rip; - ri->writefn(env, ri, value); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + ri->writefn(env, ri, value); + qemu_mutex_unlock_iothread(); + } else { + ri->writefn(env, ri, value); + } } uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip) { const ARMCPRegInfo *ri = rip; + uint32_t res; - return ri->readfn(env, ri); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + res = ri->readfn(env, ri); + qemu_mutex_unlock_iothread(); + } else { + res = ri->readfn(env, ri); + } + + return res; } void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value) { const ARMCPRegInfo *ri = rip; - ri->writefn(env, ri, value); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + ri->writefn(env, ri, value); + qemu_mutex_unlock_iothread(); + } else { + ri->writefn(env, ri, value); + } } uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) { const ARMCPRegInfo *ri = rip; + uint64_t res; + + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + res = ri->readfn(env, ri); + qemu_mutex_unlock_iothread(); + } else { + res = ri->readfn(env, ri); + } - return ri->readfn(env, ri); + return res; } void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)