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[208.118.235.17]) by mx.google.com with ESMTPS id 22si1875otc.213.2016.11.09.07.05.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 09 Nov 2016 07:05:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40457 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4URX-000665-Dv for patch@linaro.org; Wed, 09 Nov 2016 10:05:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4UKL-0000i1-3p for qemu-devel@nongnu.org; Wed, 09 Nov 2016 09:58:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4UKK-0002Lo-BA for qemu-devel@nongnu.org; Wed, 09 Nov 2016 09:58:13 -0500 Received: from mail-wm0-x234.google.com ([2a00:1450:400c:c09::234]:36860) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c4UKK-0002LK-4S for qemu-devel@nongnu.org; Wed, 09 Nov 2016 09:58:12 -0500 Received: by mail-wm0-x234.google.com with SMTP id p190so313287328wmp.1 for ; Wed, 09 Nov 2016 06:58:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zkUP0wXopLDM3MFFhG4kVPdWdJBApJtre2ZoYm+lBqg=; b=Hg9xonfDQd+VJUITzp2cAZauwvlEvgWuBytlNIUeSL20k4pofX3zgZmeDyoaP1K6Gy q0jFaalBA0si9ORte2cIz2VHo0Iuyn5MInEqNwqZ4qUxXw/t9034zcaRDhhnp+8z/CGt TqnCj0rP7EomafZPUihwhcu3Go1qfw14WZcIE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zkUP0wXopLDM3MFFhG4kVPdWdJBApJtre2ZoYm+lBqg=; b=GV1zGnMVaXGedpxDySSWIFyithSD6USIAUZDk3nQgo2P/eBjjwKr8biOY4kmXSOM3L 1ahHHLJF9qbC4/+BF5pTN9dNkWLOscKCfJk+h/UwdC2thDYFHKEJDM8jf3gZY0RB+oZQ Cl59Tnbfv4Wh7/aGbr6Oyo4RvCrMVya/gpXCmjTmKOC4JHRCxY+PIg0dt6EObG2PQvOo e1UmYJQCDnVwjMEc7G0PITd73dmx6HcLAdto1gtu5Rt+TCnDZE7eB7GhEnG5fZe1Jzc9 /GLa5wYdnD1tucF+3URDLGDR79a6CzvACE1PjEvltcDlB8rJ3ae4E1F4gwBT7jrSJ0Lb KvAQ== X-Gm-Message-State: ABUngvelrfW0tLfK9GzUBiSmc2nO671mletJR2rZTVtkVfwT/c70f0zCuJJn71PnD3rsjYIe X-Received: by 10.28.174.194 with SMTP id x185mr767275wme.4.1478703490906; Wed, 09 Nov 2016 06:58:10 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 70sm7465257wmv.1.2016.11.09.06.58.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Nov 2016 06:58:03 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 8D6C23E0426; Wed, 9 Nov 2016 14:57:57 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: pbonzini@redhat.com Date: Wed, 9 Nov 2016 14:57:39 +0000 Message-Id: <20161109145748.27282-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161109145748.27282-1-alex.bennee@linaro.org> References: <20161109145748.27282-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::234 Subject: [Qemu-devel] [PATCH v6 10/19] cputlb: add assert_cpu_is_self checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, nikunj@linux.vnet.ibm.com, Peter Crosthwaite , jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, serge.fdrv@gmail.com, bobby.prani@gmail.com, rth@twiddle.net, =?UTF-8?q?Alex=20Benn=C3=A9e?= , fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For SoftMMU the TLB flushes are an example of a task that can be triggered on one vCPU by another. To deal with this properly we need to use safe work to ensure these changes are done safely. The new assert can be enabled while debugging to catch these cases. Signed-off-by: Alex Bennée --- cputlb.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.10.1 Reviewed-by: Richard Henderson diff --git a/cputlb.c b/cputlb.c index c6e34f4..30c7c37 100644 --- a/cputlb.c +++ b/cputlb.c @@ -58,6 +58,12 @@ } \ } while (0) +#define assert_cpu_is_self(this_cpu) do { \ + if (DEBUG_TLB_GATE) { \ + g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ + } \ + } while (0) + /* statistics */ int tlb_flush_count; @@ -77,6 +83,7 @@ void tlb_flush(CPUState *cpu, int flush_global) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("(%d)\n", flush_global); memset(env->tlb_table, -1, sizeof(env->tlb_table)); @@ -93,6 +100,7 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("start\n"); for (;;) { @@ -137,6 +145,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) int i; int mmu_idx; + assert_cpu_is_self(cpu); tlb_debug("page :" TARGET_FMT_lx "\n", addr); /* Check if we need to flush due to large pages. */ @@ -174,6 +183,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) va_start(argp, addr); + assert_cpu_is_self(cpu); tlb_debug("addr "TARGET_FMT_lx"\n", addr); /* Check if we need to flush due to large pages. */ @@ -262,6 +272,8 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) int mmu_idx; + assert_cpu_is_self(cpu); + env = cpu->env_ptr; for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; @@ -293,6 +305,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) int i; int mmu_idx; + assert_cpu_is_self(cpu); + vaddr &= TARGET_PAGE_MASK; i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { @@ -352,6 +366,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE; int asidx = cpu_asidx_from_attrs(cpu, attrs); + assert_cpu_is_self(cpu); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { tlb_add_large_page(env, vaddr, size);