From patchwork Thu Dec 8 17:50:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 87322 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp973126qgi; Thu, 8 Dec 2016 09:57:29 -0800 (PST) X-Received: by 10.55.174.195 with SMTP id x186mr66211125qke.87.1481219849201; Thu, 08 Dec 2016 09:57:29 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id r68si17874171qkc.242.2016.12.08.09.57.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Dec 2016 09:57:29 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:48041 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cF2wi-00057h-KN for patch@linaro.org; Thu, 08 Dec 2016 12:57:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59639) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cF2qB-0002mV-Aj for qemu-devel@nongnu.org; Thu, 08 Dec 2016 12:50:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cF2qA-00046e-75 for qemu-devel@nongnu.org; Thu, 08 Dec 2016 12:50:43 -0500 Received: from mx1.redhat.com ([209.132.183.28]:8966) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cF2q6-00044H-RY; Thu, 08 Dec 2016 12:50:39 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CE3EEC0528A4; Thu, 8 Dec 2016 17:50:37 +0000 (UTC) Received: from kamzik.brq.redhat.com (kamzik.brq.redhat.com [10.34.1.143]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uB8HoWn2022068; Thu, 8 Dec 2016 12:50:35 -0500 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Thu, 8 Dec 2016 18:50:21 +0100 Message-Id: <20161208175030.12269-2-drjones@redhat.com> In-Reply-To: <20161208175030.12269-1-drjones@redhat.com> References: <20161208175030.12269-1-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Thu, 08 Dec 2016 17:50:37 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH kvm-unit-tests v8 01/10] arm/arm64: yield on cpu_relax X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, andre.przywara@arm.com, eric.auger@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In many tests one or more cpus wait for events from other cpus. However, with TCG, if the event triggering cpus then continue without first informing TCG it should schedule other cpus, then those other cpus may never get scheduled, and never see their events. This is because the TCG scheduler relies on either the currently running cpu to invoke an instruction that results in scheduling or for some I/O event to occur, and then to do scheduling while handling the I/O. kvm-unit-tests do not have external I/O events, so we must invoke a yielding instruction wherever needed. cpu_relax() is almost always a place it's needed. While this change is mostly for TCG, it's fine to do for KVM as well. The Linux kernel made the same change with 1baa82f4803 for armv8. As the yield instruction is also available on armv7, we make the change for both. Signed-off-by: Andrew Jones --- v8: new patch that drastically speeds up the tests with tcg, actually allowing it to complete at all after adding -nodefaults to the qemu command line... --- lib/arm/asm/barrier.h | 5 +++-- lib/arm64/asm/barrier.h | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) -- 2.9.3 diff --git a/lib/arm/asm/barrier.h b/lib/arm/asm/barrier.h index 394a4a2da26f..927cd3801dfb 100644 --- a/lib/arm/asm/barrier.h +++ b/lib/arm/asm/barrier.h @@ -1,13 +1,14 @@ #ifndef _ASMARM_BARRIER_H_ #define _ASMARM_BARRIER_H_ /* - * Adapted form arch/arm/include/asm/barrier.h + * Adapted from arch/arm/include/asm/barrier.h */ #define sev() asm volatile("sev" : : : "memory") #define wfe() asm volatile("wfe" : : : "memory") #define wfi() asm volatile("wfi" : : : "memory") -#define cpu_relax() asm volatile("" : : : "memory") +#define yield() asm volatile("yield" : : : "memory") +#define cpu_relax() yield() #define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory") #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") diff --git a/lib/arm64/asm/barrier.h b/lib/arm64/asm/barrier.h index dbdac9d339c7..4f7bb97c2279 100644 --- a/lib/arm64/asm/barrier.h +++ b/lib/arm64/asm/barrier.h @@ -7,7 +7,8 @@ #define sev() asm volatile("sev" : : : "memory") #define wfe() asm volatile("wfe" : : : "memory") #define wfi() asm volatile("wfi" : : : "memory") -#define cpu_relax() asm volatile("" : : : "memory") +#define yield() asm volatile("yield" : : : "memory") +#define cpu_relax() yield() #define isb() asm volatile("isb" : : : "memory") #define dmb(opt) asm volatile("dmb " #opt : : : "memory")