From patchwork Fri Jan 27 10:35:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 92640 Delivered-To: patch@linaro.org Received: by 10.182.3.34 with SMTP id 2csp158048obz; Fri, 27 Jan 2017 03:32:44 -0800 (PST) X-Received: by 10.55.162.138 with SMTP id l132mr7392369qke.204.1485516764932; Fri, 27 Jan 2017 03:32:44 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q58si3333538qta.119.2017.01.27.03.32.44 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 27 Jan 2017 03:32:44 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44552 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX4lm-0003WU-8f for patch@linaro.org; Fri, 27 Jan 2017 06:32:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49609) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX40M-0007fV-VB for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cX40L-0004hn-Q5 for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:43 -0500 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:38218) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cX40L-0004hR-K6 for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:41 -0500 Received: by mail-wm0-x230.google.com with SMTP id r144so130192985wme.1 for ; Fri, 27 Jan 2017 02:43:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MMvQVwwMrO8E2KpPpfeKpPjfgHAC1cH1xyqcJDBpDi0=; b=eQyhj7nyi0uIB3FJLIdhuC6YLbWjFZTdM+OWGFUcJYkI1mXmD7RD+nBWkYDI4GA8G0 mMjFuhRmRnbdH3E6s0ykfsK/HHu+a10PxuPl/nn6QYQhCtWtjlP1oZKAzEqFpeCyKafn 2ScBtNwrwrfENjWJ068zbnvmfhSFBW5XDnFG4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MMvQVwwMrO8E2KpPpfeKpPjfgHAC1cH1xyqcJDBpDi0=; b=UB88BRtB3BjTtRWAdJ0P0M6c4tJbyWCfZAqVgGwxdDJHcXVvf9vKk6UtG/z5XP7Xz9 Zm2+LbtvrTYkTer0m3UBGp+9yyVr+0ZkPQQpv0Wr5PK+3MtzdIHpkHZyiYEwspAZJG5j WCbC586OnrMSqbCf/F2DPjmFBcTVAn1YUERc5Q//nofB/Pgsd1nVb+j3UVDpm1wwBbec 6CeAj8s2KYYLP1WBT5WaD9qBLgfJZ50jVNwxUY25qjjmcGYfWvks85rxLraP51fofuyS EZu8ckjOSbxIqsRus2CU2pKt9Y5gd252sh8R5N89mpQf9cIT2E4RaAwlUmec/vnf6Zt2 wsXQ== X-Gm-Message-State: AIkVDXLTYXnq6erxgKW+LW1Q+lG3XgBrW+yLoZSKbZWM6bxAWuH0z46EhPJ2YwtSjtCPd/Lb X-Received: by 10.28.19.78 with SMTP id 75mr2763691wmt.108.1485513820533; Fri, 27 Jan 2017 02:43:40 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y80sm7257167wrb.12.2017.01.27.02.43.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jan 2017 02:43:38 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 6E7BF3E3771; Fri, 27 Jan 2017 10:35:07 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: Date: Fri, 27 Jan 2017 10:35:05 +0000 Message-Id: <20170127103505.18606-26-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170127103505.18606-1-alex.bennee@linaro.org> References: <20170127103505.18606-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [PATCH v8 25/25] tcg: enable MTTCG by default for ARM on x86 hosts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM" , =?utf-8?q?Alex_Benn=C3=A9e?= , "open list:All patches CC here" , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This enables the multi-threaded system emulation by default for ARMv7 and ARMv8 guests using the x86_64 TCG backend. This is because on the guest side: - The ARM translate.c/translate-64.c have been converted to - use MTTCG safe atomic primitives - emit the appropriate barrier ops - The ARM machine has been updated to - hold the BQL when modifying shared cross-vCPU state - defer cpu_reset to async safe work All the host backends support the barrier and atomic primitives but need to provide same-or-better support for normal load/store operations. Signed-off-by: Alex Bennée --- v7 - drop configure check for backend - declare backend memory order for x86 - declare guest memory order for ARM - add configure snippet to set TARGET_SUPPORTS_MTTCG --- configure | 6 ++++++ target/arm/cpu.h | 3 +++ tcg/i386/tcg-target.h | 16 ++++++++++++++++ 3 files changed, 25 insertions(+) -- 2.11.0 diff --git a/configure b/configure index 86fd833feb..9f2a665f5b 100755 --- a/configure +++ b/configure @@ -5879,6 +5879,7 @@ mkdir -p $target_dir echo "# Automatically generated by configure - do not modify" > $config_target_mak bflt="no" +mttcg="no" interp_prefix1=$(echo "$interp_prefix" | sed "s/%M/$target_name/g") gdb_xml_files="" @@ -5897,11 +5898,13 @@ case "$target_name" in arm|armeb) TARGET_ARCH=arm bflt="yes" + mttcg="yes" gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; aarch64) TARGET_BASE_ARCH=arm bflt="yes" + mttcg="yes" gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; cris) @@ -6066,6 +6069,9 @@ if test "$target_bigendian" = "yes" ; then fi if test "$target_softmmu" = "yes" ; then echo "CONFIG_SOFTMMU=y" >> $config_target_mak + if test "$mttcg" = "yes" ; then + echo "TARGET_SUPPORTS_MTTCG=y" >> $config_target_mak + fi fi if test "$target_user_only" = "yes" ; then echo "CONFIG_USER_ONLY=y" >> $config_target_mak diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1b0670ae11..47a42ec6d6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -29,6 +29,9 @@ # define TARGET_LONG_BITS 32 #endif +/* ARM processors have a weak memory model */ +#define TCG_DEFAULT_MO (0) + #define CPUArchState struct CPUARMState #include "qemu-common.h" diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 21d96ec35c..536190f647 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -165,4 +165,20 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +/* This defines the natural memory order supported by this + * architecture before guarantees made by various barrier + * instructions. + * + * The x86 has a pretty strong memory ordering which only really + * allows for some stores to be re-ordered after loads. + */ +#include "tcg-mo.h" + +static inline int get_tcg_target_mo(void) +{ + return TCG_MO_ALL & ~TCG_MO_LD_ST; +} + +#define TCG_TARGET_DEFAULT_MO get_tcg_target_mo() + #endif