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Wed, 22 Feb 2017 16:25:20 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 22 Feb 2017 16:25:06 +0000 Message-Id: <20170222162507.25987-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c0c::234 Subject: [Qemu-devel] [PATCH] hmp: add PC information for ARM vCPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Crosthwaite , qemu-devel@nongnu.org, "Dr. David Alan Gilbert" , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Markus Armbruster , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- cpus.c | 6 ++++++ hmp.c | 3 +++ qapi-schema.json | 14 +++++++++++++- 3 files changed, 22 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/cpus.c b/cpus.c index 559a0805bc..dc8dbfb0f0 100644 --- a/cpus.c +++ b/cpus.c @@ -1869,6 +1869,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) #elif defined(TARGET_TRICORE) TriCoreCPU *tricore_cpu = TRICORE_CPU(cpu); CPUTriCoreState *env = &tricore_cpu->env; +#elif defined(TARGET_AARCH64) + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; #endif cpu_synchronize_state(cpu); @@ -1896,6 +1899,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) #elif defined(TARGET_TRICORE) info->value->arch = CPU_INFO_ARCH_TRICORE; info->value->u.tricore.PC = env->PC; +#elif defined(TARGET_AARCH64) + info->value->arch = CPU_INFO_ARCH_ARM; + info->value->u.arm.pc = env->pc; #else info->value->arch = CPU_INFO_ARCH_OTHER; #endif diff --git a/hmp.c b/hmp.c index 2bc4f062bb..03ef6ffdd7 100644 --- a/hmp.c +++ b/hmp.c @@ -369,6 +369,9 @@ void hmp_info_cpus(Monitor *mon, const QDict *qdict) case CPU_INFO_ARCH_TRICORE: monitor_printf(mon, " PC=0x%016" PRIx64, cpu->value->u.tricore.PC); break; + case CPU_INFO_ARCH_ARM: + monitor_printf(mon, " pc=0x%016" PRIx64, cpu->value->u.arm.pc); + break; default: break; } diff --git a/qapi-schema.json b/qapi-schema.json index e9a6364b7d..650e98c950 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -1277,7 +1277,7 @@ # Since: 2.6 ## { 'enum': 'CpuInfoArch', - 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] } + 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'arm', 'other' ] } ## # @CpuInfo: @@ -1312,6 +1312,7 @@ 'ppc': 'CpuInfoPPC', 'mips': 'CpuInfoMIPS', 'tricore': 'CpuInfoTricore', + 'arm': 'CpuInfoARM', 'other': 'CpuInfoOther' } } ## @@ -1372,6 +1373,17 @@ { 'struct': 'CpuInfoTricore', 'data': { 'PC': 'int' } } ## +# @CpuInfoARM: +# +# Additional information about a virtual ARM CPU +# +# @pc: the instruction pointer +# +# Since: 2.9 +## +{ 'struct': 'CpuInfoARM', 'data': { 'pc': 'int' } } + +## # @CpuInfoOther: # # No additional information is available about the virtual CPU