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X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While the group encoding declares bit 28 a zero it is set for FCMGT (zero) Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.14.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 11990daff4..7792cea9f5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10571,10 +10571,10 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) /* AdvSIMD two reg misc FP16 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +---+---+---+-----------+---+-------------+--------+-----+------+------+ - * | 0 | 1 | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | + * | 0 | Q | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | * +---+---+---+-----------+---+-------------+--------+-----+------+------+ - * mask: 1101 1111 0111 1110 0000 1100 0000 0000 0xdf7e 0c00 - * val: 0101 1110 0111 1000 0000 1000 0000 0000 0x5e78 0800 + * mask: 1001 1111 0111 1110 0000 1100 0000 0000 0x9f7e 0c00 + * val: 0001 1110 0111 1000 0000 1000 0000 0000 0x1e78 0800 * Half-precision variants of two-reg misc. */ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) @@ -11304,7 +11304,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, - { 0x5e780800, 0xdf7e0c00, disas_simd_two_reg_misc_fp16 }, + { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; @@ -11318,6 +11318,8 @@ static void disas_data_proc_simd(DisasContext *s, uint32_t insn) if (fn) { fn(s, insn); } else { + fprintf(stderr, "%s: failed to find %#4x @ %#" PRIx64 "\n", + __func__, insn, s->pc); unallocated_encoding(s); } }