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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id h80sm15740147pfj.12.2018.01.09.23.55.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Jan 2018 23:55:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 23:55:46 -0800 Message-Id: <20180110075547.15841-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180110075547.15841-1-richard.henderson@linaro.org> References: <20180110075547.15841-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 1/2] tcg/ppc: Support tlb offsets larger than 64k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) -- 2.14.3 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 879885b68b..74f9b4aa34 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1524,16 +1524,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, /* Compensate for very large offsets. */ if (add_off >= 0x8000) { - /* Most target env are smaller than 32k; none are larger than 64k. - Simplify the logic here merely to offset by 0x7ff0, giving us a - range just shy of 64k. Check this assumption. */ - QEMU_BUILD_BUG_ON(offsetof(CPUArchState, - tlb_table[NB_MMU_MODES - 1][1]) - > 0x7ff0 + 0x7fff); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0)); + int low = (int16_t)cmp_off; + int high = cmp_off - low; + assert((high & 0xffff) == 0); + assert(cmp_off - high == (int16_t)(cmp_off - high)); + assert(add_off - high == (int16_t)(add_off - high)); + tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, base, high >> 16)); base = TCG_REG_TMP1; - cmp_off -= 0x7ff0; - add_off -= 0x7ff0; + cmp_off -= high; + add_off -= high; } /* Extraction and shifting, part 2. */