From patchwork Fri Jan 12 21:06:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 124378 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2505432qgn; Fri, 12 Jan 2018 13:06:51 -0800 (PST) X-Google-Smtp-Source: ACJfBotRzmkxhQ52taXtcJoNIKc8ktTxd/CZJwK/sGXE3IE6jKRgSTj/Bgy3qQlyxvT3hjstzxsk X-Received: by 10.129.155.67 with SMTP id s64mr8218640ywg.102.1515791211428; Fri, 12 Jan 2018 13:06:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515791211; cv=none; d=google.com; s=arc-20160816; b=sG/GpX687BbmT3P5t2WQY3vQOMkIoUdy2YBtcbZ2+tFutzOgth8XOiYcPcPFMfNvdo 6D6A1udAI0Fp0dCfm5HgniwqRUg5BLm+CGV3Y9rm4TYdi/Ev9lO5EUsPZnqfAQ/V2NiB TILba3DZ7lYdoUXQLQn2wRUOcCQI3C1iQ3JsCaWc/vh/yAqWvex9iUOQiYh/bEJOd7IC hmz0xsv9PLI28086TiSnsdQXJQ5naVgn+CXNOwx7E4xLkIket383DXMAeQ7sixMvUluL edUoA/5hSlHgprNVzo41NpDBavtVyj4EscEvAQS5VwNIF5PkH7LRwuy7ownf18jX7Ho7 FX+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=asCrjqWvKzTme/l8ME07J3gKo4r8k8Aqe9Mx+ApiovU=; b=I5yrUthQkB1g6ai5Tu9L8AOS1qLf3cTm4Ttas182GAk/WynkKVD3Aujx+o8Et/dDsi zDmhiGMBI1BNBUAhuLC/DaKX563HECYv8pO/vCeXsZJgtvCOOTaAmMiAtd95Q0/Syej/ nVeWZ6VVKcsZeCm7WFAyezOirthK8+sn69XvJQaf85kyQ6Roj0VpfwqCPRquwArCax4R lLLm4kqtdkWTpdLnzw1VhzyFiP7WqUd3bHkH+v/Vaa/cvKWGm4bdbSgMzn8CNn9ENAzd /CLmOTvs3jdk1Nn+Ez2Vd5CZ0UphRrj1CdRzeawY8bCyO4PnmNxqC/C1baFG13SHKOlt 2yLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=T51lj+NZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g37si4767272ywk.651.2018.01.12.13.06.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 12 Jan 2018 13:06:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=T51lj+NZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea6XK-0008Oe-TD for patch@linaro.org; Fri, 12 Jan 2018 16:06:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea6Wr-0008MP-Lm for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ea6Wq-0002kn-3V for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:21 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:42042) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ea6Wp-0002jf-RN for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:20 -0500 Received: by mail-pg0-x243.google.com with SMTP id q67so5326435pga.9 for ; Fri, 12 Jan 2018 13:06:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=asCrjqWvKzTme/l8ME07J3gKo4r8k8Aqe9Mx+ApiovU=; b=T51lj+NZ7KaQZCf2b0xkEfj4ZZPgdNoYBd264Hy+EfvD7bFW3ab1ekvce8FBPhpktq JH+mj/bTxyHp+Sk/w+8jgzu+tEbfP0HcM1yi6k2hwRNQIshUIW3I4qyO6EuCYE7tv97i lq87Oxie0ypgOUx5+bhKybxzMdgJtYYsPA2dQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=asCrjqWvKzTme/l8ME07J3gKo4r8k8Aqe9Mx+ApiovU=; b=OZ4W1X2prpQ30oXlyyCachXvsWRBXHoVzBJ03RZsY503pAEc97mtcDYbGJWHNf+CAr LLlIjzVmF3O1clOXMr4/OMu/UVkvMmVUyySp2SSnC50XL7c84ZoqSBf8ZirmsZSYEneC kwlW+n309+qWxmRvwSkToPJr3zqBu+4GDEG3ek6FlKnrwo9rqHKLvL62I3h+9p3rPeLF HnckZKTfQQiuX3GjaCC/YvBLnV0K8bSGDvX4kbsx8nFmy7yG7ho5M3xkSoEkBojaZZFz sBdgYqg2+DZ/FcXaS6C66YRLtVtvVyavolLpJBj9zXw9BSNq98GmHm9XUOV5LhKylu/z 8VDg== X-Gm-Message-State: AKGB3mKnez3DWkxqv9/DSN/xajkKBCbJVVBVdN5lXs7dyB8u1GHyVbPe oJYKuEB9a4r+5b7F5sv1iPD3YoXfODQ= X-Received: by 10.159.194.195 with SMTP id u3mr22056561plz.416.1515791178488; Fri, 12 Jan 2018 13:06:18 -0800 (PST) Received: from cloudburst.twiddle.net (50-78-183-178-static.hfc.comcastbusiness.net. [50.78.183.178]) by smtp.gmail.com with ESMTPSA id t80sm20197600pgb.88.2018.01.12.13.06.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Jan 2018 13:06:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 12 Jan 2018 13:06:10 -0800 Message-Id: <20180112210613.14124-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180112210613.14124-1-richard.henderson@linaro.org> References: <20180112210613.14124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 1/4] tcg/arm: Fix double-word comparisons X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The code sequence we were generating was only good for unsigned comparisons. For signed comparisions, use the sequence from gcc. Fixes booting of ppc64 firmware, with a patch changing the code sequence for ppc comparisons. Tested-by: Michael Roth Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 112 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 80 insertions(+), 32 deletions(-) -- 2.14.3 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 98a12535a5..b9890c8bd8 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -239,10 +239,11 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, } } -#define TCG_CT_CONST_ARM 0x100 -#define TCG_CT_CONST_INV 0x200 -#define TCG_CT_CONST_NEG 0x400 -#define TCG_CT_CONST_ZERO 0x800 +#define TCG_CT_CONST_ARM 0x0100 +#define TCG_CT_CONST_INV 0x0200 +#define TCG_CT_CONST_NEG 0x0400 +#define TCG_CT_CONST_INVNEG 0x0800 +#define TCG_CT_CONST_ZERO 0x1000 /* parse target specific constraints */ static const char *target_parse_constraint(TCGArgConstraint *ct, @@ -258,6 +259,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'N': /* The gcc constraint letter is L, already used here. */ ct->ct |= TCG_CT_CONST_NEG; break; + case 'M': + ct->ct |= TCG_CT_CONST_INVNEG; + break; case 'Z': ct->ct |= TCG_CT_CONST_ZERO; break; @@ -351,8 +355,7 @@ static inline int check_fit_imm(uint32_t imm) static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) { - int ct; - ct = arg_ct->ct; + int ct = arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { @@ -361,6 +364,9 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, return 1; } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { return 1; + } else if ((ct & TCG_CT_CONST_INVNEG) + && check_fit_imm(~val) && check_fit_imm(-val)) { + return 1; } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { return 1; } else { @@ -1103,6 +1109,64 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg a0) } } +static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, + const int *const_args) +{ + TCGReg al = args[0]; + TCGReg ah = args[1]; + TCGArg bl = args[2]; + TCGArg bh = args[3]; + TCGCond cond = args[4]; + int const_bl = const_args[2]; + int const_bh = const_args[3]; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_NE: + case TCG_COND_LTU: + case TCG_COND_LEU: + case TCG_COND_GTU: + case TCG_COND_GEU: + /* We perform a conditional comparision. If the high half is + equal, then overwrite the flags with the comparison of the + low half. The resulting flags cover the whole. */ + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, ah, bh, const_bh); + tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, al, bl, const_bl); + return cond; + + case TCG_COND_LT: + case TCG_COND_GE: + /* We perform a double-word subtraction and examine the result. + We do not actually need the result of the subtract, so the + low part "subtract" is a compare. For the high half we have + no choice but to compute into a temporary. */ + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, al, bl, const_bl); + tcg_out_dat_rIK(s, COND_AL, ARITH_SBC | TO_CPSR, ARITH_ADC | TO_CPSR, + TCG_REG_TMP, ah, bh, const_bh); + return cond; + + case TCG_COND_LE: + case TCG_COND_GT: + /* Similar, but with swapped arguments. And of course we must + force the immediates into a register. */ + if (const_bl) { + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP, bl); + bl = TCG_REG_TMP; + } + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, bl, al, 0); + if (const_bh) { + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP, bh); + bh = TCG_REG_TMP; + } + tcg_out_dat_rIK(s, COND_AL, ARITH_SBC | TO_CPSR, ARITH_ADC | TO_CPSR, + TCG_REG_TMP, bh, ah, 0); + return tcg_swap_cond(cond); + + default: + g_assert_not_reached(); + } +} + #ifdef CONFIG_SOFTMMU #include "tcg-ldst.inc.c" @@ -1964,22 +2028,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], arg_label(args[3])); break; - case INDEX_op_brcond2_i32: - /* The resulting conditions are: - * TCG_COND_EQ --> a0 == a2 && a1 == a3, - * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3, - * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3, - * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3), - * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3), - * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3, - */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[3], const_args[3]); - tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, - args[0], args[2], const_args[2]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], - arg_label(args[5])); - break; case INDEX_op_setcond_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, args[1], args[2], const_args[2]); @@ -1988,15 +2036,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], ARITH_MOV, args[0], 0, 0); break; + + case INDEX_op_brcond2_i32: + c = tcg_out_cmp2(s, args, const_args); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); + break; case INDEX_op_setcond2_i32: - /* See brcond2_i32 comment */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[2], args[4], const_args[4]); - tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, - args[1], args[3], const_args[3]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]], - ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])], + c = tcg_out_cmp2(s, args + 1, const_args + 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], ARITH_MOV, args[0], 0, 0); break; @@ -2093,9 +2141,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef sub2 = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } }; static const TCGTargetOpDef br2 - = { .args_ct_str = { "r", "r", "rIN", "rIN" } }; + = { .args_ct_str = { "r", "r", "rIM", "rIM" } }; static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "r", "r", "rIN", "rIN" } }; + = { .args_ct_str = { "r", "r", "r", "rIM", "rIM" } }; switch (op) { case INDEX_op_goto_ptr: