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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:31 -0800 Message-Id: <20180119045438.28582-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 09/16] target/arm: Add predicate registers for SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.14.3 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 57d805b5d8..132da359b5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -186,6 +186,15 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; +/* In AArch32 mode, predicate registers do not exist at all. */ +typedef struct ARMPredicateReg { +#ifdef TARGET_AARCH64 + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); +#else + uint64_t p[0]; +#endif +} ARMPredicateReg; + typedef struct CPUARMState { /* Regs for current mode. */ @@ -513,6 +522,9 @@ typedef struct CPUARMState { struct { ARMVectorReg zregs[32]; + /* Store FFR as pregs[16] to make it easier to treat as any other. */ + ARMPredicateReg pregs[17]; + uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len;