From patchwork Fri Jan 19 04:54:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125083 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp133065ljf; Thu, 18 Jan 2018 21:05:51 -0800 (PST) X-Google-Smtp-Source: ACJfBovlXzNhK/a0t6kaQZ+Jb5sKHXUxYSc+8mF3o12uKyqdCMeQpWmSwnhXfFRXRBRyDQMz2uGw X-Received: by 10.37.197.74 with SMTP id v71mr36325120ybe.258.1516338351037; Thu, 18 Jan 2018 21:05:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516338351; cv=none; d=google.com; s=arc-20160816; b=ScPyDm3XV+J98y5560O2+qHGQzk+2laHdTb/zptHBbOZLg76zZpWQJRROR0G+vcJ6D vzRdSihnMORb5ltmNKARJmzzffAo9w7cVDJYA8F1tFrdQG7R4n5FlE3Aqvy+rsk5dY86 EGx2n/s5GIU8dluuy38nYDFrIJbhnFXG9S0VXkWsppO1lCKaB8sMmDwRL45E3wMwJnad VEHkOAuiXlni7WLWucr4h3RVHy10dgoiIxujLuWhXNw/jnTyJOPwR68pd/hlhIxQRdTB fEOqvk6HL2twRC9QdhCrN+BYu63ZQnx3hQKAish9M91uilj0aMPW52gf+eW01UpU1K2R qH0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=MrUbi1cyBrCCWqcwORQqONge1KIiagmroE4y1V6paR4=; b=T+5yDimWFidZavatl5EsR8+4t26ZZzeI6DY7xv/om8FTKh2X/h8jDQLJp4XKdiVIjC DdMu9WM3XLJDCYVvAl6hXkR/c+1x4taOOZTeqAWDQHiLzo57tJajHqyAc0+v7kg9PkYt Ezhl/+rFGVc0E05lAIJGkdu0cR7gQZ6HbZKm1f+vrXNGe2vRjwvQELyp4w5bxG53qzHG ax/GJtHOv1RdtYNCAXt9k0tmgKBEIXla0i9wu4/iix8zbdwRSG7anJVa9FobuJmf1Yjr iAMgZfZ9Ys0r2eER3BF4Q3X2osDeAxzj48piBDomnazn0YLQumJvdD/s6XHVp3UWRzKJ UpqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fsLcWhlC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 11si355402ywz.427.2018.01.18.21.05.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 18 Jan 2018 21:05:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fsLcWhlC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOsA-0002GX-EU for patch@linaro.org; Fri, 19 Jan 2018 00:05:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhp-0002Na-4s for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhm-0000T8-1j for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:09 -0500 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35867) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhl-0000Sx-R7 for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:05 -0500 Received: by mail-pf0-x242.google.com with SMTP id 23so534528pfp.3 for ; Thu, 18 Jan 2018 20:55:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MrUbi1cyBrCCWqcwORQqONge1KIiagmroE4y1V6paR4=; b=fsLcWhlCS2JXc7ANw3xBG9PjYuUeoecaJMJbEgqLEyYBmc59SOli5MIOLa6sAMuv/t JUvZCeRDFFPPOHYovg7UFtR/sbMFLmdT7IfitWWojhIzkD3SdqF3NniiHh4RKFCwiAVU b7CuRrT8G4XXXsIbb37s4NL591LLsRtNvk8vw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MrUbi1cyBrCCWqcwORQqONge1KIiagmroE4y1V6paR4=; b=VPw7BcilUXJ9wTlZ7GMaufDPicf6S6l8GlxG/FLgK3DzURgOiyXtLLQE/UQqu3HhzW 9jirI8NMAksv2kEH2GGE7wuZpAjF9KyQELKh8DYN94MniVOk870IEYX9+CYuFshEz1nb 7az0kqVaDl087mGO3JKakqufCGcnyCjXlntwBs8z2Bqrg2PIOXEmG3vph/Lr4otaoDTq NAsJ62RLMoQHIHEnrsUfjVPLZoQmLu8qt6J/+CMmx92NKksAPbUq/MXaSDpsmr25lMl4 4an6r8A929JwkmTJygMyJUmKFfIUQDdR/nNmidq9xFPD3h9B7xRYW9SNi5bDfI1HD3JF M7jQ== X-Gm-Message-State: AKGB3mL85nzBf+Gi+GlDIo+Je84ZlzEWSjcerBSc4IRlBdP9D4IzDaw4 WWgp79/pJB/wfDNSVHO242TM1aGnsV8= X-Received: by 10.99.94.193 with SMTP id s184mr38254364pgb.397.1516337704480; Thu, 18 Jan 2018 20:55:04 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.55.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:55:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:36 -0800 Message-Id: <20180119045438.28582-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2 14/16] target/arm: Hoist store to flags output in cpu_get_tb_cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) -- 2.14.3 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index 9e673bb672..c0e5f321c5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11768,34 +11768,36 @@ static inline int fp_exception_el(CPUARMState *env) } void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) + target_ulong *cs_base, uint32_t *pflags) { ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + uint32_t flags; + if (is_a64(env)) { *pc = env->pc; - *flags = ARM_TBFLAG_AARCH64_STATE_MASK; + flags = ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ - *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); - *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); + flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); + flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); } else { *pc = env->regs[15]; - *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) + flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); if (!(access_secure_reg(env))) { - *flags |= ARM_TBFLAG_NS_MASK; + flags |= ARM_TBFLAG_NS_MASK; } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { - *flags |= ARM_TBFLAG_VFPEN_MASK; + flags |= ARM_TBFLAG_VFPEN_MASK; } - *flags |= (extract32(env->cp15.c15_cpar, 0, 2) - << ARM_TBFLAG_XSCALE_CPAR_SHIFT); + flags |= (extract32(env->cp15.c15_cpar, 0, 2) + << ARM_TBFLAG_XSCALE_CPAR_SHIFT); } - *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); + flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -11805,25 +11807,26 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending */ if (arm_singlestep_active(env)) { - *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; + flags |= ARM_TBFLAG_SS_ACTIVE_MASK; if (is_a64(env)) { if (env->pstate & PSTATE_SS) { - *flags |= ARM_TBFLAG_PSTATE_SS_MASK; + flags |= ARM_TBFLAG_PSTATE_SS_MASK; } } else { if (env->uncached_cpsr & PSTATE_SS) { - *flags |= ARM_TBFLAG_PSTATE_SS_MASK; + flags |= ARM_TBFLAG_PSTATE_SS_MASK; } } } if (arm_cpu_data_is_big_endian(env)) { - *flags |= ARM_TBFLAG_BE_DATA_MASK; + flags |= ARM_TBFLAG_BE_DATA_MASK; } - *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; if (arm_v7m_is_handler_mode(env)) { - *flags |= ARM_TBFLAG_HANDLER_MASK; + flags |= ARM_TBFLAG_HANDLER_MASK; } + *pflags = flags; *cs_base = 0; }