From patchwork Fri Jan 26 04:57:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125894 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp74257ljd; Thu, 25 Jan 2018 21:04:11 -0800 (PST) X-Google-Smtp-Source: AH8x225Ues2UgARW26B6ZGEUGsh9C7mNcQhP+osZt0gN6jhy3dcHN5Y5TXWNzPGFXKeDUzk6QtF8 X-Received: by 10.37.190.65 with SMTP id d1mr1189266ybm.38.1516943051688; Thu, 25 Jan 2018 21:04:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516943051; cv=none; d=google.com; s=arc-20160816; b=0UiJgVfnYf8VhubyDQuYlnz39+EcSMXad0/QaR6Z51l0cFn57x51i7sZdM3NQdEWPX YKYUgjWv0KN3sbyAITcIbO5MnVzg6KlJp0fgZIGVxtkEQz8I6YJe80rkZhMmMppJLpxY gIXl+OSQ8RJuGJwKq/XtfKudD6/dmDDNd/eFG9GebkHl5wxplcLjxTuY514zBFUdvsDn L6cUiSCxfFp2QZFYhnVmFiymfUeb68x69bk+YvUJ/XWxqkwAZvfdoep8ZF1zeTAVnq/D H+RbRLhJOjP8S8ccWkXPvITl1jFQneNIJ3Z9nojEfWtl8HjuA6bUlR7Rm3GcokbNplT+ H8Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7zD9ZLMaBfM3L9Jb5GjWQeL+d+QUdyrmFo8RuhCOQx8=; b=Ao9SXZIQ+k4LbW3+g1QVvCio58UAo7L5sPG4R41/AIpYJj7ZJmmfh9NUm4La5/x5Gj 1lG5XzjvD2uqEK7BvgFpY1RQgqqKVbMwy3FQjWRMjwC/oxJkOS69WKpXNgl74gqr2uTJ +mtl31Wy2w9JlRWNfHd9+hxPHSg5pEERIcXJY7i7jGh07XIiIYS9w4FA2UEsmzXz7poc M34ODuVFO5Fq7HbgyDk2WAxCK0WgQPWlM6ilmQgpgl0Ch0QNIEajXJtPZao+U5JAX9xI DaQRqeiwlreW+LwmLctUtjoYcR6VILbSpi+cTCulrnTgQu6SLo1CU0go7yiMkDIzLoaD TSrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fxs5r7Bb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o82si3532135ybb.817.2018.01.25.21.04.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 25 Jan 2018 21:04:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fxs5r7Bb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eewBP-0003Qe-4o for patch@linaro.org; Fri, 26 Jan 2018 00:04:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50954) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eewAw-0003OE-F4 for qemu-devel@nongnu.org; Fri, 26 Jan 2018 00:03:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eewAs-00004r-I0 for qemu-devel@nongnu.org; Fri, 26 Jan 2018 00:03:42 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:46162) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eewAs-0008W6-Ad for qemu-devel@nongnu.org; Fri, 26 Jan 2018 00:03:38 -0500 Received: by mail-pf0-x241.google.com with SMTP id y5so7497659pff.13 for ; Thu, 25 Jan 2018 21:03:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7zD9ZLMaBfM3L9Jb5GjWQeL+d+QUdyrmFo8RuhCOQx8=; b=fxs5r7BbunxPeOYIh3Byi+sW7152qIPt84JL85GZ74VO2Zzzed3ZlFuUgSoCP+M7Qt EXg5JtL7Ik/MKops7Ay9uWdWGm5LkLbJft6CVXiorY1+NAgz+Jzh8wO3G1gqo51rGTG6 9Qj2NvdiBL7OoCe5JcJxaWyibpAN8QkbIAIYI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7zD9ZLMaBfM3L9Jb5GjWQeL+d+QUdyrmFo8RuhCOQx8=; b=b9PHQE8tQzgQYcWeI6n1fDh1FQaqY08f8/C+Gk6ShsTXrfx5k8kn9I9GOtYHvc7AMV EtRp6Aecr5NS7YP2IoejNaORhdKNnMf2oykEjMy0L1hYSV1P0pMgVRnbLNr6M8bIS98T oKmZtpZAwaC1K2sOq9Sc63AE9kZWpKIkGIndG4nKM77RYmWOMEXINt/uN3P9/YitAkMI GqwxVt/PlZjFFMuTnn09bQVPEUAT3wgz3KeGrwK0t5M6wp0PCWEAtaYuJs8PbTXnTeyC Hu/vr+BcHLl9l4VKnxTFRskorUyB4oeMj7AobyGFzgj58bdLy2bd8x3WPTNNWbuVAJhn j05Q== X-Gm-Message-State: AKwxytd6RX1bAMVJt0SwMe2GXCZwpVRQLnbdQhL9AM5zWM+1w0vvpY96 BPuZFik6yJrhREH7lB8PhyliWNeKd8M= X-Received: by 10.101.91.66 with SMTP id y2mr15329578pgr.11.1516942702063; Thu, 25 Jan 2018 20:58:22 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id q67sm20460313pfi.164.2018.01.25.20.58.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jan 2018 20:58:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 20:57:39 -0800 Message-Id: <20180126045742.5487-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180126045742.5487-1-richard.henderson@linaro.org> References: <20180126045742.5487-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v11 17/20] target/arm: Use vector infrastructure for aa64 multiplies X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 154 +++++++++++++++++++++++++++++++++++++-------- 1 file changed, 129 insertions(+), 25 deletions(-) -- 2.14.3 Reviewed-by: Alex Bennée diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c928c4787c..64a2c2df59 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9753,6 +9753,66 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn) } } +static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_add_u8(d, d, a); +} + +static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_add_u16(d, d, a); +} + +static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_add_i32(d, d, a); +} + +static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_add_i64(d, d, a); +} + +static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_add_vec(vece, d, d, a); +} + +static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_sub_u8(d, d, a); +} + +static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_sub_u16(d, d, a); +} + +static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_sub_i32(d, d, a); +} + +static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_sub_i64(d, d, a); +} + +static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_sub_vec(vece, d, d, a); +} + /* Integer op subgroup of C3.6.16. */ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) { @@ -9771,6 +9831,52 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) .prefer_i64 = TCG_TARGET_REG_BITS == 64, .vece = MO_64 }, }; + static const GVecGen3 mla_op[4] = { + { .fni4 = gen_mla8_i32, + .fniv = gen_mla_vec, + .opc = INDEX_op_mul_vec, + .load_dest = true, + .vece = MO_8 }, + { .fni4 = gen_mla16_i32, + .fniv = gen_mla_vec, + .opc = INDEX_op_mul_vec, + .load_dest = true, + .vece = MO_16 }, + { .fni4 = gen_mla32_i32, + .fniv = gen_mla_vec, + .opc = INDEX_op_mul_vec, + .load_dest = true, + .vece = MO_32 }, + { .fni8 = gen_mla64_i64, + .fniv = gen_mla_vec, + .opc = INDEX_op_mul_vec, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .load_dest = true, + .vece = MO_64 }, + }; + static const GVecGen3 mls_op[4] = { + { .fni4 = gen_mls8_i32, + .fniv = gen_mls_vec, + .opc = INDEX_op_mul_vec, + .load_dest = true, + .vece = MO_8 }, + { .fni4 = gen_mls16_i32, + .fniv = gen_mls_vec, + .opc = INDEX_op_mul_vec, + .load_dest = true, + .vece = MO_16 }, + { .fni4 = gen_mls32_i32, + .fniv = gen_mls_vec, + .opc = INDEX_op_mul_vec, + .load_dest = true, + .vece = MO_32 }, + { .fni8 = gen_mls64_i64, + .fniv = gen_mls_vec, + .opc = INDEX_op_mul_vec, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .load_dest = true, + .vece = MO_64 }, + }; int is_q = extract32(insn, 30, 1); int u = extract32(insn, 29, 1); @@ -9828,6 +9934,19 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size); } return; + case 0x13: /* MUL, PMUL */ + if (!u) { /* MUL */ + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); + return; + } + break; + case 0x12: /* MLA, MLS */ + if (u) { + gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]); + } else { + gen_gvec_op3(s, is_q, rd, rn, rm, &mla_op[size]); + } + return; case 0x11: if (!u) { /* CMTST */ gen_gvec_op3(s, is_q, rd, rn, rm, &cmtst_op[size]); @@ -10002,23 +10121,10 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) break; } case 0x13: /* MUL, PMUL */ - if (u) { - /* PMUL */ - assert(size == 0); - genfn = gen_helper_neon_mul_p8; - break; - } - /* fall through : MUL */ - case 0x12: /* MLA, MLS */ - { - static NeonGenTwoOpFn * const fns[3] = { - gen_helper_neon_mul_u8, - gen_helper_neon_mul_u16, - tcg_gen_mul_i32, - }; - genfn = fns[size]; + assert(u); /* PMUL */ + assert(size == 0); + genfn = gen_helper_neon_mul_p8; break; - } case 0x16: /* SQDMULH, SQRDMULH */ { static NeonGenTwoOpEnvFn * const fns[2][2] = { @@ -10039,18 +10145,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genfn(tcg_res, tcg_op1, tcg_op2); } - if (opcode == 0xf || opcode == 0x12) { - /* SABA, UABA, MLA, MLS: accumulating ops */ - static NeonGenTwoOpFn * const fns[3][2] = { - { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, - { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, - { tcg_gen_add_i32, tcg_gen_sub_i32 }, + if (opcode == 0xf) { + /* SABA, UABA: accumulating ops */ + static NeonGenTwoOpFn * const fns[3] = { + gen_helper_neon_add_u8, + gen_helper_neon_add_u16, + tcg_gen_add_i32, }; - bool is_sub = (opcode == 0x12 && u); /* MLS */ - genfn = fns[size][is_sub]; read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); - genfn(tcg_res, tcg_op1, tcg_res); + fns[size](tcg_res, tcg_op1, tcg_res); } write_vec_element_i32(s, tcg_res, rd, pass, MO_32);