From patchwork Sun Jan 28 23:14:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 126097 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp1977888ljd; Sun, 28 Jan 2018 15:23:09 -0800 (PST) X-Google-Smtp-Source: AH8x2248afPxBIOAiSw1gu9z2l8FuGJ8yqSJbumoWArvLABs8UDahAxS1b9uf0JvMH+U0wFBwme1 X-Received: by 10.37.139.3 with SMTP id i3mr11207206ybl.24.1517181788953; Sun, 28 Jan 2018 15:23:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517181788; cv=none; d=google.com; s=arc-20160816; b=SsRbrNcl+vLfpH3UqeWd3SIjJef9L6NhSRZoF3gPS9uBdmnKdkIL5bRmNJ4+UBe67a et+edZkE0wr83pFbmf0rfPhj30Jkyai2aAhAmNEkXj028fbugM336214PJQh8kjwJ090 dTT2/1tt0PyMWEpz+TFSE1ZfhxMQvsjC/T+B0xBzyrVccKdrOM2pZWZk9CG1oEfMX1tQ eRdTJhJrHNp32uxhTS6ggmS3wZ+ZlS60G1dm4DuVJDhqIbsAO+ZWaJkRGCinpW99GB7A Ohye77SrFjmTLseJZCHJevPDUbRclrRGdXH7EtBm83Yf2VpV9ceq90cUg874sJltIyLe txwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=QgqzlptYXMy0QQq29+NJ7GyWaIw/cMSFnDSHHcJWSmc=; b=kHSfbwRoYfDmCvUsrNggaOpYX7kj/KHdQ2zoBdLQR/tlXJ9Tfzlam0h2fSJHDr+NME wJQ03kGOyAi7T6x3xN9Ahe/OAB8+biz0cz/hMIZ8WLW8aeL8/Lllt/qcTkPDIv40FjJz 9sL+Qi6NcRkdEy/Nl+xvAJ5ZfhEdD0o2mE6/GFtouR3aCBHBtqShz1fLIvbzp6tl6Ffh o+MiEcJBP+ABoxC/huDkroOOmKY84EiWcSQdDhmpHoqe4D7zf7agRkk2dkqfxxA+xNGi RyiqCEPzV1G/lP0JCa0Nw1xx2QrSwtS7DM0QQIOQkulbHe4SPrEVEMB2pCTFRFla3cMi ry6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V8zVsftK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k125si1374831yba.343.2018.01.28.15.23.08 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 28 Jan 2018 15:23:08 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V8zVsftK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44944 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1efwI0-0007k6-A1 for patch@linaro.org; Sun, 28 Jan 2018 18:23:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51979) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1efwAv-0002ct-K6 for qemu-devel@nongnu.org; Sun, 28 Jan 2018 18:15:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1efwAq-0008Ew-O6 for qemu-devel@nongnu.org; Sun, 28 Jan 2018 18:15:49 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:38033) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1efwAq-0008EE-FH for qemu-devel@nongnu.org; Sun, 28 Jan 2018 18:15:44 -0500 Received: by mail-pg0-x243.google.com with SMTP id y27so3008460pgc.5 for ; Sun, 28 Jan 2018 15:15:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QgqzlptYXMy0QQq29+NJ7GyWaIw/cMSFnDSHHcJWSmc=; b=V8zVsftKTrnJ1OCX4XgYM+560b1iT3MNUhQAiY2EA/t0wAFpQEsTyDsd4kE/h37/S4 W/xc+uZh0fBEZAyk/EXBPdhTkNfrVxc47bgmBUUT3+c3QPFjhHT/HcORESrXCjgCzcbW 7o5OltkNT2XBKfHYxywQ2cD9mOhUuxptvbLgA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QgqzlptYXMy0QQq29+NJ7GyWaIw/cMSFnDSHHcJWSmc=; b=meOVr3sT75yGItt6yUWNz9Q2TgUAEoj06Y/RqgcWgTmjZm/CP0tQBLuSx/QGVUEDPP 9Mgkks8Ek1Y9ICJkE7Apu/7JiIhrNWrkxYPkOMO9qPrClcAOiQzHuRrHfO3YjDd9pKpA rEE6tizRYvvtO9rz1pbzijBJ8b4it2toltjyuSPIaDQj/oWIIOcGG9dYxZlTVYodsRA5 eJWPLZSRZtvEUXgHaTeb4z4hAz6rEsPtOsTuYmnKNQDMhk2R6iToKImTbfQXhN0ODLFr MffdhYCVUbLDGRl8DvPLjIFoqnK3sSgsSxJeVDDr83/Uz7UIVLMZoO1sFe/CQbgaVTy8 lDzQ== X-Gm-Message-State: AKwxytdwThspko83b9EZT7FvKv+a4kUPUpXSIJnpL26rcFLiVVP+uIxP J1WVLvj+6B+hJHTRCaJZYRmBMvZTv9k= X-Received: by 10.99.178.19 with SMTP id x19mr19669873pge.31.1517181343095; Sun, 28 Jan 2018 15:15:43 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id r27sm26949344pfj.75.2018.01.28.15.15.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 28 Jan 2018 15:15:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 28 Jan 2018 15:14:52 -0800 Message-Id: <20180128231528.22719-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180128231528.22719-1-richard.henderson@linaro.org> References: <20180128231528.22719-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL v4 07/43] target/hppa: Implement the system mask instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 4 +++ target/hppa/op_helper.c | 14 ++++++++ target/hppa/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 113 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index c720de523b..254a4da133 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -76,3 +76,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) + +#ifndef CONFIG_USER_ONLY +DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) +#endif diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 4ab4ee8a77..1d56ba497b 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -601,3 +601,17 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c) update_fr0_op(env, GETPC()); return ret; } + +#ifndef CONFIG_USER_ONLY +target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) +{ + target_ulong psw = env->psw; + /* ??? On second reading this condition simply seems + to be undefined rather than a diagnosed trap. */ + if (nsm & ~psw & PSW_Q) { + dynexcp(env, EXCP_ILL, GETPC()); + } + env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); + return psw & PSW_SM; +} +#endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 33605a2d15..088031e7f3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -299,6 +299,10 @@ typedef struct DisasContext { updated the iaq for the next instruction to be executed. */ #define DISAS_IAQ_N_STALE DISAS_TARGET_1 +/* Similarly, but we want to return to the main loop immediately + to recognize unmasked interrupts. */ +#define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 + typedef struct DisasInsn { uint32_t insn, mask; DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, @@ -697,6 +701,14 @@ static DisasJumpType gen_illegal(DisasContext *ctx) return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } +#define CHECK_MOST_PRIVILEGED(EXCP) \ + do { \ + if (ctx->privilege != 0) { \ + nullify_over(ctx); \ + return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + } \ + } while (0) + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { /* Suppress goto_tb in the case of single-steping and IO. */ @@ -1982,6 +1994,79 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, return DISAS_NEXT; } +#ifndef CONFIG_USER_ONLY +/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ +static target_ureg extract_sm_imm(uint32_t insn) +{ + target_ureg val = extract32(insn, 16, 10); + + if (val & PSW_SM_E) { + val = (val & ~PSW_SM_E) | PSW_E; + } + if (val & PSW_SM_W) { + val = (val & ~PSW_SM_W) | PSW_W; + } + return val; +} + +static DisasJumpType trans_rsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + target_ureg sm = extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_andi_reg(tmp, tmp, ~sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_ssm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + target_ureg sm = extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ori_reg(tmp, tmp, sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr = extract32(insn, 16, 5); + TCGv_reg tmp, reg; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + reg = load_gpr(ctx, rr); + tmp = get_temp(ctx); + gen_helper_swap_system_mask(tmp, cpu_env, reg); + + /* Exit the TB to recognize new interrupts. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} +#endif /* !CONFIG_USER_ONLY */ + static const DisasInsn table_system[] = { { 0x00000000u, 0xfc001fe0u, trans_break }, /* We don't implement space register, so MTSP is a nop. */ @@ -1993,6 +2078,11 @@ static const DisasInsn table_system[] = { { 0x000008a0u, 0xfc1fffe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, +#ifndef CONFIG_USER_ONLY + { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, + { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, + { 0x00001860u, 0xffe0ffffu, trans_mtsm }, +#endif }; static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, @@ -4111,12 +4201,14 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + DisasJumpType is_jmp = ctx->base.is_jmp; - switch (ctx->base.is_jmp) { + switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: + case DISAS_IAQ_N_STALE_EXIT: copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); @@ -4124,6 +4216,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_IAQ_N_UPDATED: if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); + } else if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { + tcg_gen_exit_tb(0); } else { tcg_gen_lookup_and_goto_ptr(); }