From patchwork Tue Mar 13 15:34:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131479 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884766ljb; Tue, 13 Mar 2018 08:35:05 -0700 (PDT) X-Google-Smtp-Source: AG47ELshb+zwPmMX48n65mavtyNS0Sc6h38GtRwJvT88zeL4apcpHCCz7wbYQwcwPCS1xZEuDcfy X-Received: by 10.223.196.204 with SMTP id o12mr997411wrf.121.1520955305790; Tue, 13 Mar 2018 08:35:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955305; cv=none; d=google.com; s=arc-20160816; b=kS5gKb9RKLEzlMGZ3yNqsXLUmapaS+DDQW6oMWkQrsjQoqxFBqJ7Sjk1OWGID68tmX 5hj9CLwLj24HnWE2QeLbyM1kPDej+SSiHhzAXF2VWzVcDUl8yH91OAJVV/gSLxyoyWv8 s23X79DzfAnoKpwBe4ql0eWXu1UJ1fs9OPPVjk2imJLCUzzJ58rHgMIUyNxnbRs6o/9f 9Xb4bldqarI0O5If9PBR9dYfBJ2WMmpWhVzMr1OwqIV7xJkxwn92DkE15RPREKOxc9Xr Dx9PaBIRIGVJ394kXE8pd6vX7Hda8P6vRjcjBxuP148S7lf+cQ3Cu1n+4DkaTiCB8NXj eqLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=g1aqrBkN2F567LdqxfbyOdcy6E9Whq74r4KnWfeYgvc=; b=euBw6jT8TwAG/FSyQfiQBzywFEsdrdHPGGaRKmVUTPmOQflVNA1Fi7qKUn0NMjCgBT pRqH7QjzADgNVdhdYwucpVxIPhHfatJmS0XxgoQZbhucVTZHSqNFd2ukm2+/OpPBSXv5 en0lS03nWT0Bj0wJpGtZKtgwfIKwdhIPptWozKpaTxt6bK0ZKnaBOTCoe7y2WdvLBm7Z rvO53Aa8lnnHuQm+I0o35Kmex8r8WcSa97FTKvh+uMIXQK7TjauR5vXop8m27wFTGowf D0ANep2aIdCQYMAWFMNu5G11jl0cAKYlVys4MpBLh2mUht1l5W1LZzJBko8TODhHkq1W h5cw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 136si291524wms.222.2018.03.13.08.35.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxB-0003Fi-98; Tue, 13 Mar 2018 15:35:05 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 6/9] hw/arm/bcm2836: Create proper bcm2837 device Date: Tue, 13 Mar 2018 15:34:55 +0000 Message-Id: <20180313153458.26822-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> The bcm2837 is pretty similar to the bcm2836, but it does have some differences. Notably, the MPIDR affinity aff1 values it sets for the CPUs are 0x0, rather than the 0xf that the bcm2836 uses, and if this is wrong Linux will not boot. Rather than trying to have one device with properties that configure it differently for the two cases, create two separate QOM devices for the two SoCs. We use the same approach as hw/arm/aspeed_soc.c and share code and have a data table that might differ per-SoC. For the moment the two types don't actually have different behaviour. Signed-off-by: Peter Maydell --- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++ hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++----- hw/arm/raspi.c | 3 ++- 3 files changed, 53 insertions(+), 6 deletions(-) -- 2.16.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 9a10a76631..93248399ba 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -20,6 +20,13 @@ #define BCM283X_NCPUS 4 +/* These type names are for specific SoCs; other than instantiating + * them, code using these devices should always handle them via the + * BCM283x base class, so they have no BCM2836(obj) etc macros. + */ +#define TYPE_BCM2836 "bcm2836" +#define TYPE_BCM2837 "bcm2837" + typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; @@ -33,4 +40,16 @@ typedef struct BCM283XState { BCM2835PeripheralState peripherals; } BCM283XState; +typedef struct BCM283XInfo BCM283XInfo; + +typedef struct BCM283XClass { + DeviceClass parent_class; + const BCM283XInfo *info; +} BCM283XClass; + +#define BCM283X_CLASS(klass) \ + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) +#define BCM283X_GET_CLASS(obj) \ + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) + #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 1d1908654b..07d2705f96 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -23,6 +23,19 @@ /* "QA7" (Pi2) interrupt controller and mailboxes etc. */ #define BCM2836_CONTROL_BASE 0x40000000 +struct BCM283XInfo { + const char *name; +}; + +static const BCM283XInfo bcm283x_socs[] = { + { + .name = TYPE_BCM2836, + }, + { + .name = TYPE_BCM2837, + }, +}; + static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); @@ -156,25 +169,39 @@ static Property bcm2836_props[] = { DEFINE_PROP_END_OF_LIST() }; -static void bcm2836_class_init(ObjectClass *oc, void *data) +static void bcm283x_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + BCM283XClass *bc = BCM283X_CLASS(oc); - dc->props = bcm2836_props; + bc->info = data; dc->realize = bcm2836_realize; + dc->props = bcm2836_props; } -static const TypeInfo bcm2836_type_info = { +static const TypeInfo bcm283x_type_info = { .name = TYPE_BCM283X, .parent = TYPE_DEVICE, .instance_size = sizeof(BCM283XState), .instance_init = bcm2836_init, - .class_init = bcm2836_class_init, + .class_size = sizeof(BCM283XClass), + .abstract = true, }; static void bcm2836_register_types(void) { - type_register_static(&bcm2836_type_info); + int i; + + type_register_static(&bcm283x_type_info); + for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { + TypeInfo ti = { + .name = bcm283x_socs[i].name, + .parent = TYPE_BCM283X, + .class_init = bcm283x_class_init, + .class_data = (void *) &bcm283x_socs[i], + }; + type_register(&ti); + } } type_init(bcm2836_register_types) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 58c6e80a17..f588720138 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -136,7 +136,8 @@ static void raspi_init(MachineState *machine, int version) BusState *bus; DeviceState *carddev; - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); + object_initialize(&s->soc, sizeof(s->soc), + version == 3 ? TYPE_BCM2837 : TYPE_BCM2836); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort);