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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 38si628253qtg.435.2018.03.19.11.44.08 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:44:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43408 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzlP-0001Tp-Ue for patch@linaro.org; Mon, 19 Mar 2018 14:44:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49740) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc0-0002Ll-J0 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzbz-0007h7-Ov for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40460) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzbz-0007gJ-Hl for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:23 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzby-00031q-IQ for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:22 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:09 +0000 Message-Id: <20180319183415.1976-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If we're directly booting a Linux kernel and the CPU supports both EL3 and EL2, we start the kernel in EL2, as it expects. We must also set the SCR_EL3.HCE bit in this situation, so that the HVC instruction is enabled rather than UNDEFing. Otherwise at least some kernels will panic when trying to initialize KVM in the guest. Signed-off-by: Peter Maydell Message-id: 20180313153458.26822-4-peter.maydell@linaro.org --- hw/arm/boot.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.16.2 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e21a92f972..9319b12fcd 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -729,6 +729,11 @@ static void do_cpu_reset(void *opaque) assert(!info->secure_board_setup); } + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* If we have EL2 then Linux expects the HVC insn to work */ + env->cp15.scr_el3 |= SCR_HCE; + } + /* Set to non-secure if not a secure boot */ if (!info->secure_boot && (cs != first_cpu || !info->secure_board_setup)) {