From patchwork Tue Mar 20 13:41:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132146 Delivered-To: patches@linaro.org Received: by 10.46.84.29 with SMTP id i29csp880437ljb; Tue, 20 Mar 2018 06:41:18 -0700 (PDT) X-Google-Smtp-Source: AG47ELuPsjdX1VndxQG6rsi+Joqrij3m8bsn+0YznoRE5lB8/hZ4D1/A7eGfNy+XXZ4ynefr+MSA X-Received: by 10.28.172.196 with SMTP id v187mr2347126wme.69.1521553278196; Tue, 20 Mar 2018 06:41:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521553278; cv=none; d=google.com; s=arc-20160816; b=KJIvDvaWjgXZhuwtyo2ieIQTfRbgHs+XxvBe/iX0yYFnKKODLtpav+2LuxLtP6fYvn IDfnpPeX/Pc2/8qxYCqL9KPe829T4FBtLaETkRhYz37JAsqIKNedTN/kt6KnpMsOXewg mGlCgmBsQzENhIlRcTIIN7GnZpCLGZ4GLI5IVSM1z2r/FAC83+CTebUdwSqAG/0KgmJ6 VZqwpCRLbJNh9PYXGEbqfyO0kuvS2iRocpMe2sfHy95zmYgYK1gdCG5N17Wa4A8h4Q3c EuCvO6QKpaEgJtCaUesRloWakcfdwdQdqClLNw1+Z/YL9Y/440ULgXlOyimzlEwg1WVt 7tDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=edgydhp+zW1vB7+kgJzn06q30B4HyUexobq4kbva/nc=; b=CrdoYMMqwU7ILE8YOWgUITVYrm4bPCTeGSNCBWYGJm5baewENxv9fA1QUH0ovZ+ANF eGudvm8oQd/9M2wMpQZ1SepeZRGyLTechn1MkxjnNVrZQGTaxR55CMNlrQHsxxp7o7eX URFIcu+OVC3e6i31kQfT+IoE0/nf2QWZDFDG5EKHSOOckernmJ3hlNkBIIfa+7jDZjVa dD4YpSIAlT4+O8MfV1abV5s0q1tYt/1YAVjRbumKaxzhaN+Mcp+fBEeiq/UeGLSkgE2Y 114RHqJRc8oXtTbOuXaw+Xxr9N6cm5a7ou4g8kDgoAG5kAQxWCqn1e1Z9ZH06a0OCmcv RP0g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 198si1284822wmo.87.2018.03.20.06.41.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Mar 2018 06:41:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eyHVt-00044f-Jw; Tue, 20 Mar 2018 13:41:17 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH for-2.12 2/4] target/arm: Factor out code to calculate FSR for debug exceptions Date: Tue, 20 Mar 2018 13:41:12 +0000 Message-Id: <20180320134114.30418-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180320134114.30418-1-peter.maydell@linaro.org> References: <20180320134114.30418-1-peter.maydell@linaro.org> When a debug exception is taken to AArch32, it appears as a Prefetch Abort, and the Instruction Fault Status Register (IFSR) must be set. The IFSR has two possible formats, depending on whether LPAE is in use. Factor out the code in arm_debug_excp_handler() which picks an FSR value into its own utility function, update it to use arm_fi_to_lfsc() and arm_fi_to_sfsc() rather than hard-coded constants, and use the correct condition to select long or short format. In particular this fixes a bug where we could select the short format because we're at EL0 and the EL1 translation regime is not using LPAE, but then route the debug exception to EL2 because of MDCR_EL2.TDE and hand EL2 the wrong format FSR. Signed-off-by: Peter Maydell --- target/arm/internals.h | 25 +++++++++++++++++++++++++ target/arm/op_helper.c | 12 ++---------- 2 files changed, 27 insertions(+), 10 deletions(-) -- 2.16.2 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/internals.h b/target/arm/internals.h index 47cc224a46..8ce944b7a0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -763,4 +763,29 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) } } +/* Return the FSR value for a debug exception (watchpoint, hardware + * breakpoint or BKPT insn) targeting the specified exception level. + */ +static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) +{ + ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; + int target_el = arm_debug_target_el(env); + bool using_lpae = false; + + if (target_el == 2 || arm_el_is_aa64(env, target_el)) { + using_lpae = true; + } else { + if (arm_feature(env, ARM_FEATURE_LPAE) && + (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + using_lpae = true; + } + } + + if (using_lpae) { + return arm_fi_to_lfsc(&fi); + } else { + return arm_fi_to_sfsc(&fi); + } +} + #endif diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 4b123d2bd6..75efff9edf 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1330,11 +1330,7 @@ void arm_debug_excp_handler(CPUState *cs) cs->watchpoint_hit = NULL; - if (extended_addresses_enabled(env)) { - env->exception.fsr = (1 << 9) | 0x22; - } else { - env->exception.fsr = 0x2; - } + env->exception.fsr = arm_debug_exception_fsr(env); env->exception.vaddress = wp_hit->hitaddr; raise_exception(env, EXCP_DATA_ABORT, syn_watchpoint(same_el, 0, wnr), @@ -1354,11 +1350,7 @@ void arm_debug_excp_handler(CPUState *cs) return; } - if (extended_addresses_enabled(env)) { - env->exception.fsr = (1 << 9) | 0x22; - } else { - env->exception.fsr = 0x2; - } + env->exception.fsr = arm_debug_exception_fsr(env); /* FAR is UNKNOWN, so doesn't need setting */ raise_exception(env, EXCP_PREFETCH_ABORT, syn_breakpoint(same_el),