From patchwork Tue Mar 20 13:41:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132147 Delivered-To: patches@linaro.org Received: by 10.46.84.29 with SMTP id i29csp880456ljb; Tue, 20 Mar 2018 06:41:19 -0700 (PDT) X-Google-Smtp-Source: AG47ELui48NqGYSEr65z+1BevxvZMzQuj0JffcIDkBkdYQy9aSaO4v+NpVSalQzOEsXc4XdzuDG6 X-Received: by 10.223.209.132 with SMTP id h4mr2113514wri.12.1521553278931; Tue, 20 Mar 2018 06:41:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521553278; cv=none; d=google.com; s=arc-20160816; b=u4ZCodLFGYe6t4oqMIlnBuR8s3jRDw0yd40YO8GIrCkLr7sFRggq1h7idunikHErPZ 0iqasisZc163hvzhTcLIA4wwPQgNhCjoLfthzDTBho+iSftQmo4x0MwTZxLloZt1if9K JLCi7FdMKODuJdhqGTsJbBdQW6MySjqOpqFq8WbpDIZWDVOKn+uVhchG0xZDAVmIEJgL JAhOD9Qw969UTIAan8q4Jl+9fd98qJp0Jrij9ucZFVydTlV/Qkt6ZxcuOMQ0PvxZyzlj KndpPc9G4pjWwW6FwMrdkOH9Y0nZJtkPYGyR5ucddoehAxLfAE8RN2cz71Klue7vUENe R9JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=W27jp9ZZKBsVTF4/ByPRGcfZ/hlRyxCxkyjcFXZiww4=; b=rb2v6+RMTzUEAcaixTUnYJ4Eh6aV/CVOYBn/9D1BqCvsojOQ8c3c/eZ++rlbEOC8JD kibUD7iJKkFK80INA6kAtwejJSTHHaFABi/nxmiC99XjwImcIc+NgGZOfRNtMdt9ziZD RZ7UjQxPV9+QOzqOicEJQXCCGE6WGi5TaAphJQkZV7ZGE7tomjsods7qTOKuDT5qWT3S l+jWjzLodnkY0PVE/dFLoiPTmEv59h2idYX4etp7zwciX0HzRvDZI35mR9j/Zs3qPDw6 hGL3lqTQiZN6V2L9IuXIw9xsl6t5cvQm4g/XW16KLUoCj+5sW8eZ1yI7L1U9o6xXH3hP gzDg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 22si1425731wrw.420.2018.03.20.06.41.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Mar 2018 06:41:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eyHVu-00045A-Fa; Tue, 20 Mar 2018 13:41:18 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH for-2.12 3/4] target/arm: Set FSR for BKPT, BRK when raising exception Date: Tue, 20 Mar 2018 13:41:13 +0000 Message-Id: <20180320134114.30418-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180320134114.30418-1-peter.maydell@linaro.org> References: <20180320134114.30418-1-peter.maydell@linaro.org> Now that we have a helper function specifically for the BRK and BKPT instructions, we can set the exception.fsr there rather than in arm_cpu_do_interrupt_aarch32(). This allows us to use our new arm_debug_exception_fsr() helper. In particular this fixes a bug where we were hardcoding the short-form IFSR value, which is wrong if the target exception level has LPAE enabled. Fixes: https://bugs.launchpad.net/qemu/+bug/1756927 Signed-off-by: Peter Maydell --- target/arm/helper.c | 1 - target/arm/op_helper.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) -- 2.16.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/helper.c b/target/arm/helper.c index 09893e3f72..dcb8476d9e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7910,7 +7910,6 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) offset = 0; break; case EXCP_BKPT: - env->exception.fsr = 2; /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 75efff9edf..8e1e521193 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -488,6 +488,8 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, */ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) { + /* FSR will only be used if the debug target EL is AArch32. */ + env->exception.fsr = arm_debug_exception_fsr(env); raise_exception(env, EXCP_BKPT, syndrome, arm_debug_target_el(env)); }