From patchwork Tue Apr 10 12:17:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133082 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1242868ljb; Tue, 10 Apr 2018 05:26:51 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/m+C+LsYYKN+3zfaLxvNoGQzsyyMu96Rv/ZJVwEjC7kTZ2Pz84ucI/PlbUVGSDyEvDfsX8 X-Received: by 10.200.112.71 with SMTP id y7mr302289qtm.208.1523363211872; Tue, 10 Apr 2018 05:26:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523363211; cv=none; d=google.com; s=arc-20160816; b=dCvQ0rNpVeND1HdiPx1k4PSXC/+Xz0tQXBBY5KhOuVCNVR7RgNwB4nMKUHXeNvIZWv fwEpDT+6Q9l6NZhnClPf/q6e7UZTZAA6drgmowpFcvO9375t3CokKrP/xQAcPrqf97j7 5EUL/ZRa6KAFPRtUb4zUM/5EM1TuEtfnxxYJECZsRdCBp/qU7UY3B1Mneu/xDB69zNjm RV51XeWK4Q6LVGBqSalfxn2OscRf0/BjSHeWASVw1koKsXfepYw8mr0O7X6lfRqYCnsJ qrjSOM5VqRORC4NDbQKnVbEcM5laLOIHUUJkyS9ka3gtwIgCeYRNZo2LEoRvNa2rOi8T 9Zcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=TV6OPiQSRFkEJAy7kmpf7niluOb92774QkZUqYWyqho=; b=JVZtS7xt6zkQRgkORtlLULu83Co2VJtvcTVX1MxGK4BZFxwfbkk4ibw0xHXgM21hcv eFBXwS3poLqDUXmxpSHdnH5pM0Pj+X6CA4Dw5YtNu3c4sYyiWHi3Wo/QxDRE3Zj/c47g 8qQcQdQLxqqmPdZX7vCR8DZZigPF4cJCIKvtineREK7ZgzvJBDOXVavW+JgqG3f/voX9 Tith1WXlT8stmpEBUZbyWYbHfHJAE0JjIkbclvWnL6CZdH/IX2RjbDGI+XhMblJmjLMw cPm2op7m6k/KhkL5yYBNxqLnai2T6owWDaF4bj1spwN2s/TxUX572FWvWez4uiL9XJOk fS6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 27si1072252qtu.362.2018.04.10.05.26.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 10 Apr 2018 05:26:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40730 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f5sMN-000723-8w for patch@linaro.org; Tue, 10 Apr 2018 08:26:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56968) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f5sDU-0007vc-Bs for qemu-devel@nongnu.org; Tue, 10 Apr 2018 08:17:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f5sDT-0000kr-GY for qemu-devel@nongnu.org; Tue, 10 Apr 2018 08:17:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40762) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f5sDT-0000iH-9X for qemu-devel@nongnu.org; Tue, 10 Apr 2018 08:17:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f5sDI-0007aN-PO for qemu-devel@nongnu.org; Tue, 10 Apr 2018 13:17:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 10 Apr 2018 13:17:15 +0100 Message-Id: <20180410121724.8549-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180410121724.8549-1-peter.maydell@linaro.org> References: <20180410121724.8549-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/12] target-arm: Check undefined opcodes for SWP in A32 decoder X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Onur Sahin Make sure we are not treating architecturally Undefined instructions as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A specification. Bits [21:20] must be zero for this to be a SWP or SWPB. We also choose to UNDEF for the architecturally UNPREDICTABLE case of bits [11:8] not being zero. Signed-off-by: Onur Sahin [PMM: tweaked commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.16.2 diff --git a/target/arm/translate.c b/target/arm/translate.c index fc03b5b8c8..db1ce6510a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9237,11 +9237,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } tcg_temp_free_i32(addr); - } else { + } else if ((insn & 0x00300f00) == 0) { + /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx + * - SWP, SWPB + */ + TCGv taddr; TCGMemOp opc = s->be_data; - /* SWP instruction */ rm = (insn) & 0xf; if (insn & (1 << 22)) { @@ -9259,6 +9262,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) get_mem_index(s), opc); tcg_temp_free(taddr); store_reg(s, rd, tmp); + } else { + goto illegal_op; } } } else {