| Message ID | 20180512003217.9105-2-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Fixups for ARM_FEATURE_V8_FP16 | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Adding the fp16 moves to/from general registers. > > Cc: qemu-stable@nongnu.org > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/translate-a64.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 4d1b220cc6..5b8cf75e9f 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -5700,6 +5700,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) > tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); > clear_vec_high(s, true, rd); > break; > + case 3: > + /* 16 bit */ > + tmp = tcg_temp_new_i64(); > + tcg_gen_ext16u_i64(tmp, tcg_rn); > + write_fp_dreg(s, rd, tmp); > + tcg_temp_free_i64(tmp); > + break; > + default: > + g_assert_not_reached(); > } > } else { > TCGv_i64 tcg_rd = cpu_reg(s, rd); > @@ -5717,6 +5726,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) > /* 64 bits from top half */ > tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); > break; > + case 3: > + /* 16 bit */ > + tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); > + break; > + default: > + g_assert_not_reached(); > } > } > } > @@ -5756,6 +5771,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) > case 0xa: /* 64 bit */ > case 0xd: /* 64 bit to top half of quad */ > break; > + case 0x6: /* 16-bit float, 32-bit int */ > + case 0xe: /* 16-bit float, 64-bit int */ > + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { > + break; > + } > + /* fallthru */ > default: > /* all other sf/type/rmode combinations are invalid */ > unallocated_encoding(s); -- Alex Bennée
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4d1b220cc6..5b8cf75e9f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5700,6 +5700,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); clear_vec_high(s, true, rd); break; + case 3: + /* 16 bit */ + tmp = tcg_temp_new_i64(); + tcg_gen_ext16u_i64(tmp, tcg_rn); + write_fp_dreg(s, rd, tmp); + tcg_temp_free_i64(tmp); + break; + default: + g_assert_not_reached(); } } else { TCGv_i64 tcg_rd = cpu_reg(s, rd); @@ -5717,6 +5726,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) /* 64 bits from top half */ tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); break; + case 3: + /* 16 bit */ + tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); + break; + default: + g_assert_not_reached(); } } } @@ -5756,6 +5771,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) case 0xa: /* 64 bit */ case 0xd: /* 64 bit to top half of quad */ break; + case 0x6: /* 16-bit float, 32-bit int */ + case 0xe: /* 16-bit float, 64-bit int */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ default: /* all other sf/type/rmode combinations are invalid */ unallocated_encoding(s);
Adding the fp16 moves to/from general registers. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-a64.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.17.0