From patchwork Sat May 12 00:32:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135579 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1557997lji; Fri, 11 May 2018 17:37:21 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrjhjQfVjf2htlJcR7Qw63/jC2KwC3YOOGH4Twbi/SnOxqHl7eBFJQpdyk8ZJJFcnLRj6am X-Received: by 2002:a0c:ae51:: with SMTP id z17-v6mr563598qvc.235.1526085441231; Fri, 11 May 2018 17:37:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526085441; cv=none; d=google.com; s=arc-20160816; b=yqxYy7M/Nv33PiEEPzIklwQ9ecXwGRGjDWuDaLPKqgnL6yqGRirdaYHU1afPb+lqrs ygB0yue8DlUYrr4Uz8FEGo7GAiBFmAB25SlX3p+uoVV2KeeghYvHbG5h8kLjOASucHBA SVzthBjY9Vh8pIn59X63LnuXOkDqmGnRmTJ+yYmeWfBGh3kv++t6Jf/74sQ9DYO4a/qQ KSU1NAMg1t6q5Ssrt6yl6RMxZe2SLBOLHb8sZdLYz66IcALJqq/HvY1rD2id/JXlQY3t OVqvZ7z3tCW8lwp8oFoer4AG0kuecXZmWRS2FNM1k6PWjyvswos+IwffNwpyYW4bspHZ MXNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lrDMCiJQcx5bgYFEZNLR3lTllZ2WXdzXlFUjge+eWHE=; b=AF7/mPMhIhlwywPC3Cvp03cu4jobLmVSkESToqBvz3Z/2RSHGJPa2yQ5v7Cfn5lfMO wMF6fSLOfMBx+KTUqfYmPEK345Di2elA6YUq2Dcs3FwoOq5CS8zHXfUOcm5I890RpVOF efHg5laS86E7aZg6p9N0WDSvN6+fJni5QDiM7fmtEFcYQuvnxAZpinLXMV/GuT9WiHsX KMGuXA2WjpoZ88xNRHKbOMXScER9mZH0EdL5xjxOYoFbbFI5pPX+XbDxPOyXvb/3xJ/J IC+V/MQvXwYfmSJCNvNCHI3PHZD7CqKtuaRQ30d9TFtJknliZ2kRH//ybpzXhjY5rWZW AHmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UpDQhsPX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w5-v6si4372250qve.271.2018.05.11.17.37.21 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 11 May 2018 17:37:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UpDQhsPX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58623 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHIXI-0002aC-Mu for patch@linaro.org; Fri, 11 May 2018 20:37:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59218) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHISg-0006c9-Kw for qemu-devel@nongnu.org; Fri, 11 May 2018 20:32:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fHISf-0008CT-6W for qemu-devel@nongnu.org; Fri, 11 May 2018 20:32:34 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36085) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fHISe-0008CD-VM for qemu-devel@nongnu.org; Fri, 11 May 2018 20:32:33 -0400 Received: by mail-pg0-x244.google.com with SMTP id z70-v6so3075049pgz.3 for ; Fri, 11 May 2018 17:32:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lrDMCiJQcx5bgYFEZNLR3lTllZ2WXdzXlFUjge+eWHE=; b=UpDQhsPXgiwESHMHd1JOwb7y7IJXdVTRvEMGVXyRbN8B01/UaFKtbLjHlGjMb66hXI JIdO5rbcBNBW41tdhNaSBnsi7kvFhliV9uxAyFnP31iyFV4hdpo28HG+pAMXXprp/aBK d+7CFGKjiviGsd4DUR6hHs+o2KCsFiFNZ+MAY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lrDMCiJQcx5bgYFEZNLR3lTllZ2WXdzXlFUjge+eWHE=; b=EhQTAzqKzczV0hLJ3osWsaVqGYnfgrggr7H8wCxK3MpNHAC6DsuzxhLncgBZ0Wid2A d4ebOSC1egMjFboJ+iprJjdHukh/swNjN0NfCRbAWBFU/70en0+cZpB+SeUCeTRVyKoy UbXW7M9xNN95sm633vm4BKyGKoXkY61U+F69vQJR9FaUdADlR7Kr1kZ3VFdHfSpK8WvV z7FumBizhpmwohzfTYMneEHB5RcStaFfnh2Ls6xicZmMzn3+L9njDZVx+T5K9157UhwF T6vTthRYlASfE97QUf8QWo6ilkvfCaPSYQXhkBDG5BN6GBOsm73qQWPEOCvAHhoqdMLa hQRw== X-Gm-Message-State: ALKqPwdUc4BuDLinUDnXfWZp687RWBtzNdqXwmokZhp5/IjHZYUcZjCd O3P5HBdvgHhm72xr+P59frpzSTfHt6w= X-Received: by 2002:a62:f713:: with SMTP id h19-v6mr918589pfi.165.1526085151671; Fri, 11 May 2018 17:32:31 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id v186-v6sm7599735pfb.45.2018.05.11.17.32.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:32:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:32:14 -0700 Message-Id: <20180512003217.9105-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512003217.9105-1-richard.henderson@linaro.org> References: <20180512003217.9105-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v4 08/11] target/arm: Implement FCMP for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée These where missed out from the rest of the half-precision work. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée [rth: Diagnose lack of FP16 before fp_access_check] Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 + target/arm/helper-a64.c | 10 +++++ target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++-------- 3 files changed, 83 insertions(+), 17 deletions(-) -- 2.17.0 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index b8028ac98c..9d3a907049 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -19,6 +19,8 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) +DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 549ed3513e..4f8034c513 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -85,6 +85,16 @@ static inline uint32_t float_rel_to_flags(int res) return flags; } +uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status) +{ + return float_rel_to_flags(float16_compare_quiet(x, y, fp_status)); +} + +uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status) +{ + return float_rel_to_flags(float16_compare(x, y, fp_status)); +} + uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status) { return float_rel_to_flags(float32_compare_quiet(x, y, fp_status)); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a79c09eda2..c078a54fa5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4712,14 +4712,14 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) } } -static void handle_fp_compare(DisasContext *s, bool is_double, +static void handle_fp_compare(DisasContext *s, int size, unsigned int rn, unsigned int rm, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags = tcg_temp_new_i64(); - TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); - if (is_double) { + if (size == MO_64) { TCGv_i64 tcg_vn, tcg_vm; tcg_vn = read_fp_dreg(s, rn); @@ -4736,19 +4736,35 @@ static void handle_fp_compare(DisasContext *s, bool is_double, tcg_temp_free_i64(tcg_vn); tcg_temp_free_i64(tcg_vm); } else { - TCGv_i32 tcg_vn, tcg_vm; + TCGv_i32 tcg_vn = tcg_temp_new_i32(); + TCGv_i32 tcg_vm = tcg_temp_new_i32(); - tcg_vn = read_fp_sreg(s, rn); + read_vec_element_i32(s, tcg_vn, rn, 0, size); if (cmp_with_zero) { - tcg_vm = tcg_const_i32(0); + tcg_gen_movi_i32(tcg_vm, 0); } else { - tcg_vm = read_fp_sreg(s, rm); + read_vec_element_i32(s, tcg_vm, rm, 0, size); } - if (signal_all_nans) { - gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); - } else { - gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + + switch (size) { + case MO_32: + if (signal_all_nans) { + gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } else { + gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } + break; + case MO_16: + if (signal_all_nans) { + gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } else { + gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } + break; + default: + g_assert_not_reached(); } + tcg_temp_free_i32(tcg_vn); tcg_temp_free_i32(tcg_vm); } @@ -4769,16 +4785,35 @@ static void handle_fp_compare(DisasContext *s, bool is_double, static void disas_fp_compare(DisasContext *s, uint32_t insn) { unsigned int mos, type, rm, op, rn, opc, op2r; + int size; mos = extract32(insn, 29, 3); - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ + type = extract32(insn, 22, 2); rm = extract32(insn, 16, 5); op = extract32(insn, 14, 2); rn = extract32(insn, 5, 5); opc = extract32(insn, 3, 2); op2r = extract32(insn, 0, 3); - if (mos || op || op2r || type > 1) { + if (mos || op || op2r) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: + size = MO_32; + break; + case 1: + size = MO_64; + break; + case 3: + size = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4787,7 +4822,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn) return; } - handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); + handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); } /* Floating point conditional compare @@ -4801,16 +4836,35 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) unsigned int mos, type, rm, cond, rn, op, nzcv; TCGv_i64 tcg_flags; TCGLabel *label_continue = NULL; + int size; mos = extract32(insn, 29, 3); - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ + type = extract32(insn, 22, 2); rm = extract32(insn, 16, 5); cond = extract32(insn, 12, 4); rn = extract32(insn, 5, 5); op = extract32(insn, 4, 1); nzcv = extract32(insn, 0, 4); - if (mos || type > 1) { + if (mos) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: + size = MO_32; + break; + case 1: + size = MO_64; + break; + case 3: + size = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4831,7 +4885,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) gen_set_label(label_match); } - handle_fp_compare(s, type, rn, rm, false, op); + handle_fp_compare(s, size, rn, rm, false, op); if (cond < 0x0e) { gen_set_label(label_continue);