From patchwork Mon Jun 4 08:45:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 137619 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1244134lji; Mon, 4 Jun 2018 01:47:24 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKFHGFQB2wwIXvxWDJXUfQv4YbU6tOakKFrG/UizxeaFaDBOsTg3nQ1VN9I/ito1CwSEvfl X-Received: by 2002:a37:7441:: with SMTP id p62-v6mr18526224qkc.262.1528102044505; Mon, 04 Jun 2018 01:47:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528102044; cv=none; d=google.com; s=arc-20160816; b=0W1EtTuHyF6uY1oa6kD2K+45Q3Zc2tVEPlW4TTb475MtOwtYpk8tkkZL3KMJKhkS3T 5Nkd2xsjmtBBPPZuJL51jzjF6gf+EguJDu0bl/IteAgGl4zahdoddwU3PoxZuuasw/Hx 71whTrm8lm3bq3pg93M5MfP/By22iFp4zYHq/fuo8tFEvpconQFLhjAIiaZ/MwORcZfF /3VMVN90JP6CT3sUkT1ZEX7m639rUYzwPhwF3+/sUtFLGjzXl1MLmy6oPv1Fn6WacAp7 KhPjo21F/qBBrYyirxEqYSnDYcJ+29nFn3XAJFq/V5tpc4ycju+XXBb2TaRqA+mNUbSH 7nIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=qoflnn/+CoQHDdLMo5zOqb+MPob670VX6BU+bDGma2Q=; b=ladr8hE6vg4La015v64mHGP1p1WoCfcKj51hR8o+OIDzoC0gKyqR8PVYBgoYs6AAI2 KSBJUfUMQ3cPAvpJYyttZ1kCbCixLCqHrfaOIR+bW8h70vYNJY/AS/EPcQfWpXEZcssP cbaAWAJMSqxM1RJnWrp5vecoGwEI8B5qGF3L/+41r8RKiOhN5Wy2WQT4F9rt8Vd0eZfH o1swlURYYjN6nVwQndAnvfweVG//z/v0ZInycF76f7xIVdjs5oXvoCjj3N2GwTvsSoaX CvkczmIR/ByddbXl0x+9rEPj8x2b6p+c8cJwbRc+10gJfze44DU0ANO20vhVTwIc6C2g wptw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=tjaxJa/i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w64-v6si12164972qkd.78.2018.06.04.01.47.24 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 04 Jun 2018 01:47:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=tjaxJa/i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:38353 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fPl9A-0006N3-2p for patch@linaro.org; Mon, 04 Jun 2018 04:47:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58448) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fPl7O-00060a-8x for qemu-devel@nongnu.org; Mon, 04 Jun 2018 04:45:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fPl7N-0002o7-8y for qemu-devel@nongnu.org; Mon, 04 Jun 2018 04:45:34 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:34888) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fPl7G-0002WB-Ny; Mon, 04 Jun 2018 04:45:26 -0400 Received: by mail-pg0-x22c.google.com with SMTP id 15-v6so13842209pge.2; Mon, 04 Jun 2018 01:45:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=qoflnn/+CoQHDdLMo5zOqb+MPob670VX6BU+bDGma2Q=; b=tjaxJa/i76zJcctsVYEzvT1M/dwl6UVRNSsDLif6gt7l9nupSUR8FTRWeRJPZ7B5IS LYBxKEilyxyZ+/snBE/3hpLqXPxc3Ypy/3iTi5VbHtV1PNhk8CDwbPc72xYMOT+rw/8I tLS/yNobh1LM/peBS0XnvZ4N46TplcYXgt7+rzCag3v2pX374bxVncLJDN5V029GeI+0 ZDB+Si830IAPVF1mMUTbIDIcq1AqjteAplPFYuyTDjVmPMvahcpdkwNbQEPhJhZ1dDFF 3egCVEzD+hgmtaKnzrh6G5SQuIyLzbOsHyOPYKgkbEebARUv/b468fGOulvRBMBt0B0K EQaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=qoflnn/+CoQHDdLMo5zOqb+MPob670VX6BU+bDGma2Q=; b=qSk+4zVkSkDzomztXrSrizSih41gEvHt+u8OSg8T2FAYoVLPLEih8IdxMGPiL+mlrj 1TOyhwuOAW/VuE9T4nLAHW7XAfXTHfoqhbh0ju3brDXFqE7eMaK4iAkrbokKRn8TSEE0 EYHJym+SwhBiOkLMYly4GV9/ls+0gyWTKAJKKbVMt8nPDXZEv6plcAj5supk71q7kXJh C31ElAGfyyqiaYvNnGmT+zgDHNWSyP+EuKHZLkDeZLme3UlXjO8QX0mZ0PggMTTQ8C+u SXkji+jMCUMflH9kTWwjjfM2d5rOfiAn0J7ak5zh1nzDxNVasNDCBFY2ZSX0tzl0caN4 MXFw== X-Gm-Message-State: ALKqPwc1hCLWwIVWkwPSuGK3SAe3o0jdv8f8xKLGA19s5HtkANxnkJIZ Gj98w7dXcngqkSOZOFpnkn4= X-Received: by 2002:a63:6107:: with SMTP id v7-v6mr16888146pgb.264.1528101925313; Mon, 04 Jun 2018 01:45:25 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.19]) by smtp.gmail.com with ESMTPSA id 84-v6sm18462953pfl.186.2018.06.04.01.45.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Jun 2018 01:45:24 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Mon, 04 Jun 2018 18:15:16 +0930 From: Joel Stanley To: David Gibson , Alexander Graf , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Date: Mon, 4 Jun 2018 18:15:13 +0930 Message-Id: <20180604084513.8298-1-joel@jms.id.au> X-Mailer: git-send-email 2.17.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH v3] target/ppc: Allow privileged access to SPR_PCR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Ellerman , Michael Neuling , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Greg Kurz Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The powerpc Linux kernel[1] and skiboot firmware[2] recently gained changes that cause the Processor Compatibility Register (PCR) SPR to be cleared. These changes cause Linux to fail to boot on the Qemu powernv machine with an error: Trying to write privileged spr 338 (0x152) at 0000000030017f0c With this patch Qemu makes this register available as a hypervisor privileged register. Note that bits set in this register disable features of the processor. Currently the only register state that is supported is when the register is zeroed (enable all features). This is sufficient for guests to once again boot. [1] https://lkml.kernel.org/r/20180518013742.24095-1-mikey@neuling.org [2] https://patchwork.ozlabs.org/patch/915932/ Signed-off-by: Joel Stanley --- v2: - Change error message to say Invalid instead of Unimplemented - Fix compile warning on other powerpc targets, thanks patchew v3: - Mask against pcr_mask before storing - Drop check for non-zero value --- target/ppc/helper.h | 1 + target/ppc/misc_helper.c | 9 +++++++++ target/ppc/translate_init.inc.c | 9 +++++++-- 3 files changed, 17 insertions(+), 2 deletions(-) -- 2.17.0 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 19453c68138a..d751f0e21909 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -17,6 +17,7 @@ DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) +DEF_HELPER_2(store_pcr, void, env, tl) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 8c8cba5cc6f1..b88493009609 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "qemu/error-report.h" #include "helper_regs.h" @@ -98,6 +99,14 @@ void helper_store_ptcr(CPUPPCState *env, target_ulong val) tlb_flush(CPU(cpu)); } } + +void helper_store_pcr(CPUPPCState *env, target_ulong value) +{ + PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + + env->spr[SPR_PCR] = value & pcc->pcr_mask; +} #endif /* defined(TARGET_PPC64) */ void helper_store_pidr(CPUPPCState *env, target_ulong val) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index ab782cb32aaa..1a89017ddea8 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -424,6 +424,10 @@ static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); } +static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); +} #endif #endif @@ -7957,11 +7961,12 @@ static void gen_spr_power6_common(CPUPPCState *env) #endif /* * Register PCR to report POWERPC_EXCP_PRIV_REG instead of - * POWERPC_EXCP_INVAL_SPR. + * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. */ - spr_register(env, SPR_PCR, "PCR", + spr_register_hv(env, SPR_PCR, "PCR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pcr, 0x00000000); }