From patchwork Thu Jun 21 01:53:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 139421 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1481366lji; Wed, 20 Jun 2018 19:12:06 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI0UwQg0W9BT3QwkuKR0pZ5jc5VWyXkO07VBoFJgKCIlk31SPX8B8TaB8ssgYJ6dvbQjM4A X-Received: by 2002:ac8:18d7:: with SMTP id o23-v6mr21893274qtk.28.1529547126219; Wed, 20 Jun 2018 19:12:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529547126; cv=none; d=google.com; s=arc-20160816; b=xWsBTGSeUZqAOW5WYO62C4XOv4b94YWH0vToc+8h4DOjW4m3FtJZsdt90SKMKt2bNv CG8Es9nbklpahSfy5oQm9QH3Pm+1xpFXIMDo+8JTvnBRP60AqSJWCvyck/6qzxV0bRNi LMH3x5BOq54i8422EnmoQpklXIEXwrMY1HfrnYwuk8z5xYntWe8HbDscKR6rqzMvCgxa LF/f+9JW2Mm0354cKvyrzQf6nWhWQxO3mgAvMaMuDuwzx4CnUdhuYK7CDz3kiMR6oPDP rKj5X7quNeaxGbMjYLnPX5oYz6CPDel+MXbTY8uZ4HGCgS0zmAYVUPaPG53j7YtW9DeZ casA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=YM1glD7stHNvZqQN3AWRG/IvykMWfYM5AgvXp5srQR0=; b=J35V8NNgeD/NmI5wzdOnIgcyUgntqGImLEiEzDH1+keY/tnqBn/TDBtSTSEFAgF5GH o5uLvEEFKtX2MWzDg+iWXtj10cQuRc9UpY6J3ZAzac3bi2bhhGluk1ZidkiWb12oxGja 8ymFc1MmMP/XkVeg/D31UtNWLRzUTvK4SXLTt0qArMDxhN88odW4w1kZODEM96pUpUX4 a02VUgC/qXMD0+Wc82x/tQYTNU9npaVMFtZ9ON5F8h00i0ZjD/2Uhm5aCMRHHfxtRUJS jmhHs368DlVpZEuWYCgBBlMSLnQpYBbfOBJHm6Egbo7hoXSOFZwwjN7qegcXsXtiWIOK CUiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aEjp4Cfg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s11-v6si3351124qvn.166.2018.06.20.19.12.06 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 20 Jun 2018 19:12:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aEjp4Cfg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52570 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVp4v-0000b2-JU for patch@linaro.org; Wed, 20 Jun 2018 22:12:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39368) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVooE-0004gg-0s for qemu-devel@nongnu.org; Wed, 20 Jun 2018 21:54:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVooC-0003KT-35 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 21:54:50 -0400 Received: from mail-pl0-x22b.google.com ([2607:f8b0:400e:c01::22b]:39902) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fVooB-0003K2-QY for qemu-devel@nongnu.org; Wed, 20 Jun 2018 21:54:47 -0400 Received: by mail-pl0-x22b.google.com with SMTP id s24-v6so752994plq.6 for ; Wed, 20 Jun 2018 18:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YM1glD7stHNvZqQN3AWRG/IvykMWfYM5AgvXp5srQR0=; b=aEjp4CfgU4VlL5WiVthx2wYXBFXcqdH3LemPp3n9hn72GsrgZO9zhZXM+KscqZIoj1 7pfReehU4z2UIPP69KrvHf3LWpVVV9z1luhhmRwN8ASS9HBycIiFiktvdO07gKkDEOwl I9B5bXQE0Uz8Olv89i8RyWCyvjjtP2TAdKYgI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YM1glD7stHNvZqQN3AWRG/IvykMWfYM5AgvXp5srQR0=; b=s8xG3+Q7ww7COIxaLusHmoNtPTwHg5BI3K94urs4+BcrSfUbvFdWG49BWO8z6NlfmK PAMz4KO/IJ3nq9JiKfnO6eZlQUxslp5Qc5y+Ezh4B71G3qtV+0Hwd1RY3x2QM3C1lhJu CV4fpToLuu5KzRDc202ZpjJ22s/vM2ATpvEJujQ7btvxIs1OXmzOs9awFWQXotCmDnSJ x4+ZCySXwjifdMQZlX4KEtIIQetQlG1Rf5g5ImjCMiMEz/pDrSLv/wsPJAcMX/3RORT/ gp8GBxkXRP5qo8W9w0LlAu6ojseWf/Cs6Iu4N5oC1qM2O/tOrVgz2RBnbzNko6JfE6Yn E4bQ== X-Gm-Message-State: APt69E3fXhw2qwbw4v5VroPMD02HlJ9cUC9AhX5vtUS24KJpZTytPRyb cshwjhBgVhs6FtSAJ0223NUPtlttC8E= X-Received: by 2002:a17:902:b40f:: with SMTP id x15-v6mr26487854plr.270.1529546086488; Wed, 20 Jun 2018 18:54:46 -0700 (PDT) Received: from cloudburst.twiddle.net (mta-98-147-121-51.hawaii.rr.com. [98.147.121.51]) by smtp.gmail.com with ESMTPSA id a27-v6sm6187946pfc.18.2018.06.20.18.54.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Jun 2018 18:54:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 20 Jun 2018 15:53:46 -1000 Message-Id: <20180621015359.12018-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621015359.12018-1-richard.henderson@linaro.org> References: <20180621015359.12018-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22b Subject: [Qemu-devel] [PATCH v5 22/35] target/arm: Implement SVE floating-point trig multiply-add coefficient X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 4 +++ target/arm/sve_helper.c | 70 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 27 +++++++++++++++ target/arm/sve.decode | 3 ++ 4 files changed, 104 insertions(+) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 44a98440c9..aca137fc37 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1037,6 +1037,10 @@ DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_ld1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 06e963e9c2..3dc35d8b12 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3428,6 +3428,76 @@ DO_FPCMP_PPZ0_ALL(sve_fcmlt0, DO_FCMLT) DO_FPCMP_PPZ0_ALL(sve_fcmeq0, DO_FCMEQ) DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE) +/* FP Trig Multiply-Add. */ + +void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) +{ + static const float16 coeff[16] = { + 0x3c00, 0xb155, 0x2030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x3c00, 0xb800, 0x293a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + }; + intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float16); + intptr_t x = simd_data(desc); + float16 *d = vd, *n = vn, *m = vm; + for (i = 0; i < opr_sz; i++) { + float16 mm = m[i]; + intptr_t xx = x; + if (float16_is_neg(mm)) { + mm = float16_abs(mm); + xx += 8; + } + d[i] = float16_muladd(n[i], mm, coeff[xx], 0, vs); + } +} + +void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) +{ + static const float32 coeff[16] = { + 0x3f800000, 0xbe2aaaab, 0x3c088886, 0xb95008b9, + 0x36369d6d, 0x00000000, 0x00000000, 0x00000000, + 0x3f800000, 0xbf000000, 0x3d2aaaa6, 0xbab60705, + 0x37cd37cc, 0x00000000, 0x00000000, 0x00000000, + }; + intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float32); + intptr_t x = simd_data(desc); + float32 *d = vd, *n = vn, *m = vm; + for (i = 0; i < opr_sz; i++) { + float32 mm = m[i]; + intptr_t xx = x; + if (float32_is_neg(mm)) { + mm = float32_abs(mm); + xx += 8; + } + d[i] = float32_muladd(n[i], mm, coeff[xx], 0, vs); + } +} + +void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) +{ + static const float64 coeff[16] = { + 0x3ff0000000000000ull, 0xbfc5555555555543ull, + 0x3f8111111110f30cull, 0xbf2a01a019b92fc6ull, + 0x3ec71de351f3d22bull, 0xbe5ae5e2b60f7b91ull, + 0x3de5d8408868552full, 0x0000000000000000ull, + 0x3ff0000000000000ull, 0xbfe0000000000000ull, + 0x3fa5555555555536ull, 0xbf56c16c16c13a0bull, + 0x3efa01a019b1e8d8ull, 0xbe927e4f7282f468ull, + 0x3e21ee96d2641b13ull, 0xbda8f76380fbb401ull, + }; + intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float64); + intptr_t x = simd_data(desc); + float64 *d = vd, *n = vn, *m = vm; + for (i = 0; i < opr_sz; i++) { + float64 mm = m[i]; + intptr_t xx = x; + if (float64_is_neg(mm)) { + mm = float64_abs(mm); + xx += 8; + } + d[i] = float64_muladd(n[i], mm, coeff[xx], 0, vs); + } +} + /* * Load contiguous data, protected by a governing predicate. */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 0c55501935..fb225d56a1 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3597,6 +3597,33 @@ DO_PPZ(FCMNE_ppz0, fcmne0) #undef DO_PPZ +/* + *** SVE floating-point trig multiply-add coefficient + */ + +static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a, uint32_t insn) +{ + static gen_helper_gvec_3_ptr * const fns[3] = { + gen_helper_sve_ftmad_h, + gen_helper_sve_ftmad_s, + gen_helper_sve_ftmad_d, + }; + + if (a->esz == 0) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz = vec_full_reg_size(s); + TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16); + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + status, vsz, vsz, a->imm, fns[a->esz - 1]); + tcg_temp_free_ptr(status); + } + return true; +} + /* *** SVE Floating Point Accumulating Reduction Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 5dea2e5e88..e29c598783 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -796,6 +796,9 @@ FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 +# SVE floating-point trig multiply-add coefficient +FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx + ### SVE FP Multiply-Add Group # SVE floating-point multiply-accumulate writing addend