From patchwork Fri Jun 29 16:17:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 140628 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1041932ljj; Fri, 29 Jun 2018 09:17:36 -0700 (PDT) X-Google-Smtp-Source: AAOMgpf2e6YWqs/KlkIiIxTI5OePPUTT+9aT/dDVpm3Qja8Ku/DaKTsoCFa0VJfaFsE1zFRahN5X X-Received: by 2002:adf:c00b:: with SMTP id z11-v6mr12264737wre.268.1530289056186; Fri, 29 Jun 2018 09:17:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530289056; cv=none; d=google.com; s=arc-20160816; b=X7Qeys30X8u0CKRLVZ0X+VUEkqVWV+rhmAc63jsKG/MEFHjUEivj2W8PRHN5QOBeNl bngfJ/PF/f8tKYaUUsy/9mewYFND29r/ym1gl06fFsVysQrgpWj0GRWpiNbCNMXWN36l KhP6glu+v/Hh3CID5q4HkOE+KlEY+19nGA0u+4Y5n8Jvg8UonRYvBbkunycorDdxvmE+ k/nRMewukUlB0Pa8N8qxU/f+NpOUi2FpuTjCyCoT+FI2a8vVnm+tW6RrqSq0M5HEL/Bt bvp62q9jDxN9pTvaBlGqLMlqNr4KNkOujfL1etgzG258zqp0+nZ0Ndm4PaG5+X/U4MN3 b81Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:arc-authentication-results; bh=61H8h6GUCmDzUos1DkQRzMR4o7ILsqzJYLKiHRpqir4=; b=aK6Wr6Xo3UudKVTay25d76xMKu+WxNweQ9V8kJaHrem4xH0Dmxmc2fGrF6FVag0+n8 zKhU9oyQhYjEk9fqIMME8OWWlYSIZn00dCQyhEsB02R65DDELGgHrX8C/1ik1ynj0Ffc vzMlJToIy3PPCcNEQQJw7jvg+7Zd+CQLDsgRZDpa0/0cUI01a93mN5s3StOFAOxlNYnM VZoAuk+Zu5w6//j5Z8bf1t0uXExx9KT+J+XYI14u8PHtb8L72l4ZkbOP+DRmBrGqiOrC 3xxfcXUvC50+5Snbv2sbzVR2Z4tKlgVyYaWbsJNFrxBKM7VU00vulVwECC8E8XFGUrDu SCgw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id t84-v6si1155486wmg.43.2018.06.29.09.17.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 29 Jun 2018 09:17:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fYw5U-0004vC-4g; Fri, 29 Jun 2018 17:17:32 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , Laurent Vivier , patches@linaro.org Subject: [PATCH for-3.0] accel/tcg: Don't treat invalid TLB entries as needing recheck Date: Fri, 29 Jun 2018 17:17:31 +0100 Message-Id: <20180629161731.16239-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In get_page_addr_code() when we check whether the TLB entry is marked as TLB_RECHECK, we should not go down that code path if the TLB entry is not valid at all (ie the TLB_INVALID bit is set). Reported-by: Laurent Vivier Signed-off-by: Peter Maydell --- This fixes the abort that Laurent was seeing with his m68k test case. accel/tcg/cputlb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 Tested-by: Laurent Vivier Reviewed-by: Richard Henderson diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index eebe97dabb7..a55296583b9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -967,7 +967,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) } } - if (unlikely(env->tlb_table[mmu_idx][index].addr_code & TLB_RECHECK)) { + if (unlikely((env->tlb_table[mmu_idx][index].addr_code & + (TLB_RECHECK | TLB_INVALID_MASK)) == TLB_RECHECK)) { /* * This is a TLB_RECHECK access, where the MMU protection * covers a smaller range than a target page, and we must