From patchwork Tue Jul 3 05:57:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140905 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp783713ljj; Mon, 2 Jul 2018 23:23:25 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdtCnXkGIrtR2ilRRp5K4krqYtD3xx2PuHxc6LzP1OHtNOjNNulVV+WwWX29EPWTrlLEAYs X-Received: by 2002:a37:9605:: with SMTP id y5-v6mr23796508qkd.236.1530599005801; Mon, 02 Jul 2018 23:23:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530599005; cv=none; d=google.com; s=arc-20160816; b=jgYQNzj2OkChpwqTxJ9xIY7bRABiMntHMQ6da2S3bYLUyXd+jhpW++bSAMzMo82AR4 wd4VbP3FKKAatYOdbaOzYzAbWEwyEo7Nd7En3sk79yM3Zl6cl3eLuojURwbV9BjzzuxH JdtJzJ1z1RV5OFqncqq5pEpTkjgxODEtFgS4NLbHydQY3+yZz2RGswvUvNQpQUYjwzr6 RJz4eBPJhP2Xw7OEjDUiLaG7NsPI+E7btRBESnOrS1pyKimiG5lypTk7mVpFKgN5htfZ Tr7+5Wwp9MWXCaW2hJVJklT2LYbTLeTdWeAQ3YsXvtQLula/hsq6bHb13Cnr/6OBoMaR Xpgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=TZgZAxqw/hZLiVnhjbkqkVWxlTEF/NewFWmVrfHa5go=; b=0WuvfaTua486/L8njwF8LUCZXmroXaAQnHBlBK8J6o8geFuvSLd7gO6shLlESTpdaP DRo0EwnbYNepb03MgzSt8uYSWOMHXFgMvc00pQl14sCViwOGNqRSzCG29XnVf3eDu1un zmYB8r7C/vcTmhjEVdi/8OHyXnSAESYg4urCFudqGKFrt0nRAfIOcMRz6+t8Ggt4DGuM y4/Krrsm6dPM8Zcah7H8B5Ky8yECf2ZqOGoEVoDGwQrU0H++f8OFv9eT4k2ypm5wtGv9 xisZD3U7zFMK3K02HCjA+umHcF6ibacOk/2YZHFgtEPIIcMByTZ1S6bhGIeLjHPrXAVO cMVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BiZ3C1T9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v184-v6si356610qkd.398.2018.07.02.23.23.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:23:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BiZ3C1T9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38072 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEij-0005XN-7O for patch@linaro.org; Tue, 03 Jul 2018 02:23:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKV-0002rC-P7 for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKS-0006xs-IT for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:23 -0400 Received: from ozlabs.org ([203.11.71.1]:48151) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKR-0006uF-P6; Tue, 03 Jul 2018 01:58:20 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM95kgWz9s9y; Tue, 3 Jul 2018 15:58:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597493; bh=b9K6lgAlIlXGzW0zb2bBBQrlnAX0Fz3I1exeWmRL6qk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BiZ3C1T91IVzidnguaTAMzKkEVb63YvVUJuEIFDVFTeAAJGT/O1EURTIl2tufHags wax2xynIWN/Oc4Ugbb+sR5Z6MP9Ae6mmGofKX5soAgikNGAym0WFtzcBnyF+09XhuK v8kTfrJektBuTaIcTnIgpZyCs4r5zlh65bAyeeLc= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:44 +1000 Message-Id: <20180703055804.13449-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 15/35] target/ppc: Remove POWERPC_EXCP_STCX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- linux-user/ppc/cpu_loop.c | 121 +++++++------------------------------- target/ppc/cpu.h | 5 -- target/ppc/translate.c | 14 ----- 3 files changed, 22 insertions(+), 118 deletions(-) -- 2.17.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 2fb516cb00..133a87f349 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -65,99 +65,23 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) return -1; } -static int do_store_exclusive(CPUPPCState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val, val2 __attribute__((unused)) = 0; - int flags; - int segv = 0; - - addr = env->reserve_ea; - page_addr = addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags = page_get_flags(page_addr); - if ((flags & PAGE_READ) == 0) { - segv = 1; - } else { - int reg = env->reserve_info & 0x1f; - int size = env->reserve_info >> 5; - int stored = 0; - - if (addr == env->reserve_addr) { - switch (size) { - case 1: segv = get_user_u8(val, addr); break; - case 2: segv = get_user_u16(val, addr); break; - case 4: segv = get_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv = get_user_u64(val, addr); break; - case 16: { - segv = get_user_u64(val, addr); - if (!segv) { - segv = get_user_u64(val2, addr + 8); - } - break; - } -#endif - default: abort(); - } - if (!segv && val == env->reserve_val) { - val = env->gpr[reg]; - switch (size) { - case 1: segv = put_user_u8(val, addr); break; - case 2: segv = put_user_u16(val, addr); break; - case 4: segv = put_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv = put_user_u64(val, addr); break; - case 16: { - if (val2 == env->reserve_val2) { - if (msr_le) { - val2 = val; - val = env->gpr[reg+1]; - } else { - val2 = env->gpr[reg+1]; - } - segv = put_user_u64(val, addr); - if (!segv) { - segv = put_user_u64(val2, addr + 8); - } - } - break; - } -#endif - default: abort(); - } - if (!segv) { - stored = 1; - } - } - } - env->crf[0] = (stored << 1) | xer_so; - env->reserve_addr = (target_ulong)-1; - } - if (!segv) { - env->nip += 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - void cpu_loop(CPUPPCState *env) { CPUState *cs = CPU(ppc_env_get_cpu(env)); target_siginfo_t info; - int trapnr; + int trapnr, sig; target_ulong ret; for(;;) { + bool arch_interrupt; + cpu_exec_start(cs); trapnr = cpu_exec(cs); cpu_exec_end(cs); process_queued_cpu_work(cs); - switch(trapnr) { + arch_interrupt = true; + switch (trapnr) { case POWERPC_EXCP_NONE: /* Just go on */ break; @@ -524,26 +448,15 @@ void cpu_loop(CPUPPCState *env) } env->gpr[3] = ret; break; - case POWERPC_EXCP_STCX: - if (do_store_exclusive(env)) { - info.si_signo = TARGET_SIGSEGV; + case EXCP_DEBUG: + sig = gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo = sig; info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->nip; + info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_DEBUG: - { - int sig; - - sig = gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - info.si_signo = sig; - info.si_errno = 0; - info.si_code = TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } + } else { + arch_interrupt = false; } break; case EXCP_INTERRUPT: @@ -551,12 +464,22 @@ void cpu_loop(CPUPPCState *env) break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); + arch_interrupt = false; break; default: cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); break; } process_pending_signals(env); + + /* Most of the traps imply a transition through kernel mode, + * which implies an REI instruction has been executed. Which + * means that RX and LOCK_ADDR should be cleared. But there + * are a few exceptions for traps internal to QEMU. + */ + if (arch_interrupt) { + env->reserve_addr = -1; + } } } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 973cf44cda..4edcf62cf7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -196,7 +196,6 @@ enum { /* QEMU exceptions: special cases we want to stop translation */ POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ - POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ }; /* Exceptions error codes */ @@ -994,10 +993,6 @@ struct CPUPPCState { /* Reservation value */ target_ulong reserve_val; target_ulong reserve_val2; - /* Reservation store address */ - target_ulong reserve_ea; - /* Reserved store source register and size */ - target_ulong reserve_info; /* Those ones are used in supervisor mode only */ /* machine state register */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c7b9d226eb..03e8c5df03 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3201,19 +3201,6 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) #endif -#if defined(CONFIG_USER_ONLY) -static void gen_conditional_store(DisasContext *ctx, TCGv EA, - int reg, int memop) -{ - TCGv t0 = tcg_temp_new(); - - tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); - tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); - tcg_temp_free(t0); - gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); -} -#else static void gen_conditional_store(DisasContext *ctx, TCGv EA, int reg, int memop) { @@ -3244,7 +3231,6 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA, gen_set_label(l2); tcg_gen_movi_tl(cpu_reserve, -1); } -#endif #define STCX(name, memop) \ static void gen_##name(DisasContext *ctx) \