From patchwork Tue Jul 3 05:57:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140899 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp768118ljj; Mon, 2 Jul 2018 23:08:28 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdvsjyPzKOl8Dm01WKQQRyMq2VedkSKzspZZ+9uI5vcBSqufsIRatqE0gVXOQzerxthovQc X-Received: by 2002:ac8:174a:: with SMTP id u10-v6mr19081542qtk.367.1530598108398; Mon, 02 Jul 2018 23:08:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530598108; cv=none; d=google.com; s=arc-20160816; b=SN5SMPqunsNAnwP2+ha1Ec5zU2wToVmho4FkZrSpkjnj/+eGozkIPxleImseEXP3uQ TJo7cCPi1Pxqyi3HZKy+p0cF/niX6N/Iz1mvsvXgxv8o8/NvqUunmyErpM3k+Tq78tw+ /Zq2/6PscWycFOHQ2eH3Xa0DKs3cip3I1aE1kBEtGWunU2Zx47bmIORViYSBIy2Zs2re vQYx3ycvPfzrFGF1zpH/LuSXH8fUEnCavj/OF4ZhBBI6hegYYVLNWkVHzEf/IRf9wOER rez20/WOmP9I44kmx2YUMQ2uKVHkjgc1t2l13xO41R1PL4c7tWKuuAKSssK/zD6E2vzw iHfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=dwYs5YSf+jutZyAdGBbEg9XfxsF9RIINPa/eHcDKyvk=; b=xhqw/Sj8+W7KP8dmrnx8OsNI85hIfY9PVKxWG0pU8t7fk4iM1N0LcOQ7XnMRm3lILR XeJwKk4IUPa7Of6vHJT8OxQ5/5H69AW2pEr9XGR9nBiPT2Dwuzm/1YNsziotDWs/xAOr cpKy6xnr4BV/EOG1APXAsjzxlCWx05nAhFJ0S2h7uEWxh1vWRLzhVMYnC8nIPtENaN/G ScklNxCZBzMKdzKC+qJ7lFhfi34lKCQ5L51iPMI1stymzcvkabq4id103CHwLZUxJ2gz yszpUD9/KRlgF31vZEn+CsBCxjrebWTvRBISyVnHyLfKLCmLIY/TXIx6U6/VgIRMV+RF c3HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=N9pkRrvf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q53-v6si352455qte.315.2018.07.02.23.08.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:08:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=N9pkRrvf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37985 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEUF-0002Bp-QU for patch@linaro.org; Tue, 03 Jul 2018 02:08:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39829) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKW-0002rG-Mu for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKT-0006yn-PD for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:24 -0400 Received: from ozlabs.org ([203.11.71.1]:46381) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKS-0006um-Vy; Tue, 03 Jul 2018 01:58:21 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM96KkZz9s9G; Tue, 3 Jul 2018 15:58:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597493; bh=82ysa0rNFDy/kfS7HaxFjTLARUbZmvxjdH6OTbl17BM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N9pkRrvfVc5BBktEXEI6go+Y311we8KEUjf1qp1Ee01Yq1UtD/iAP6Ie0N04Uvjvb qgV4ACqutqeRcNDTa8ltHPYfH2R5xJGXHcCQ046rVzVFppgn+a6F/AhAqKALbL8IY7 FBOuC/xVQEnkUVP7o3PVpjWE7jehN6MgoxQ9lmwg= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:47 +1000 Message-Id: <20180703055804.13449-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 18/35] target/ppc: Split out gen_ld_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Move the guts of LD_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 105 ++++++++++++++++++++--------------------- 1 file changed, 52 insertions(+), 53 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f48fcbeefb..361b178db8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3095,61 +3095,60 @@ LARX(lbarx, DEF_MEMOP(MO_UB)) LARX(lharx, DEF_MEMOP(MO_UW)) LARX(lwarx, DEF_MEMOP(MO_UL)) -#define LD_ATOMIC(name, memop, tp, op, eop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - int len = MEMOP_GET_SIZE(memop); \ - uint32_t gpr_FC = FC(ctx->opcode); \ - TCGv EA = tcg_temp_local_new(); \ - TCGv_##tp t0, t1; \ - \ - gen_addr_register(ctx, EA); \ - if (len > 1) { \ - gen_check_align(ctx, EA, len - 1); \ - } \ - t0 = tcg_temp_new_##tp(); \ - t1 = tcg_temp_new_##tp(); \ - tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ - \ - switch (gpr_FC) { \ - case 0: /* Fetch and add */ \ - tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 1: /* Fetch and xor */ \ - tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 2: /* Fetch and or */ \ - tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 3: /* Fetch and 'and' */ \ - tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 8: /* Swap */ \ - tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 4: /* Fetch and max unsigned */ \ - case 5: /* Fetch and max signed */ \ - case 6: /* Fetch and min unsigned */ \ - case 7: /* Fetch and min signed */ \ - case 16: /* compare and swap not equal */ \ - case 24: /* Fetch and increment bounded */ \ - case 25: /* Fetch and increment equal */ \ - case 28: /* Fetch and decrement bounded */ \ - gen_invalid(ctx); \ - break; \ - default: \ - /* invoke data storage error handler */ \ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ - } \ - tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ - tcg_temp_free_##tp(t0); \ - tcg_temp_free_##tp(t1); \ - tcg_temp_free(EA); \ +static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) +{ + uint32_t gpr_FC = FC(ctx->opcode); + TCGv EA = tcg_temp_new(); + TCGv src, dst; + + gen_addr_register(ctx, EA); + dst = cpu_gpr[rD(ctx->opcode)]; + src = cpu_gpr[rD(ctx->opcode) + 1]; + + memop |= MO_ALIGN; + switch (gpr_FC) { + case 0: /* Fetch and add */ + tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 1: /* Fetch and xor */ + tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Fetch and or */ + tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 3: /* Fetch and 'and' */ + tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 8: /* Swap */ + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Fetch and max unsigned */ + case 5: /* Fetch and max signed */ + case 6: /* Fetch and min unsigned */ + case 7: /* Fetch and min signed */ + case 16: /* compare and swap not equal */ + case 24: /* Fetch and increment bounded */ + case 25: /* Fetch and increment equal */ + case 28: /* Fetch and decrement bounded */ + gen_invalid(ctx); + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + tcg_temp_free(EA); } -LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) -#if defined(TARGET_PPC64) -LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) +static void gen_lwat(DisasContext *ctx) +{ + gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); +} + +#ifdef TARGET_PPC64 +static void gen_ldat(DisasContext *ctx) +{ + gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); +} #endif #define ST_ATOMIC(name, memop, tp, op) \