From patchwork Tue Aug 14 12:42:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 144160 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4310509ljj; Tue, 14 Aug 2018 05:43:01 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzEj9pPQrwMLrOcY8o9Bk8Ena/14I2GIzN+QVguOW//uos2E+6R+pcEAamBOnIr+Lbc12a1 X-Received: by 2002:adf:bacf:: with SMTP id w15-v6mr14064042wrg.203.1534250581712; Tue, 14 Aug 2018 05:43:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534250581; cv=none; d=google.com; s=arc-20160816; b=MluFYmLu4XAIhAjMd8lfd0i6j7EzkhTVkOP60zbXL4CtycgMkHKhuny6EOZjvXH6s+ tfvw8x/D7GTOhamFq41BK/00IQpdMouXenT7gRR4hr0mJqMfB8sIayn0xs8kVlUCIInc /hwN1wlinfymi4IYHtdq/Z1+m8kC9wObwpTZme1zT9BtMWhbifrPBziL8N+oPw1FgQUG xCM+wwGeXoHIohdXjr44YZJ2W9wEDxfr9Tik0cKi98qwFA2K8Faf/U409apOj3ctHyfO Vu2zVgy5zA+sgwXH0ua6m0QTur2yHFHc3cmOalzywO5g3IYa3aVl16TGqqxS3IBJPeAz 7EfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=YW6XVXxQcUaASyPFJ9Tyi1emgbEmVvzRU91WNAzj894=; b=dLAxiWW5B5zhSywPKZDbBtz3TKoyo8zqqFXQyHh8WNnAr+nHAUYA4s7hS3O2Bqkjhv IzAwmriknZ2Tztd7zZ5EMBj0W7hqaAaVdEuUT12oz4hOau/gDLndJ2uURy4qzg6jpoxT njzxEoCUvGbXJEPk6jWOpBnBD1a+sDpPIwUAwwb/v9F93o8NDSNKpfm2NEAM9CpewyS/ P1uYJ2/wazV/5NtX9ARHP8BzOfVN4AK3XR+sSdvHXEiMwY92pqYZftRGK8VpKooCtdBn KsWIvj80FqAqBQYId03VI9ZoT7tTVAYnPp48czQrRJs3JuDeCd9VGsXpgYyIQqkz07/E cu2Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id q126-v6si8638177wma.157.2018.08.14.05.43.01 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 Aug 2018 05:43:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYf7-0006nt-5Q; Tue, 14 Aug 2018 13:43:01 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Luc Michel , edgari@xilinx.com Subject: [PATCH 02/10] target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs Date: Tue, 14 Aug 2018 13:42:46 +0100 Message-Id: <20180814124254.5229-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> ARMCPRegInfo structs will not default to .cp = 15 if they are ARM_CP_STATE_BOTH, but not if they are ARM_CP_STATE_AA32 (because a coprocessor number of 0 is valid for AArch32). We forgot to explicitly set .cp = 15 for the HMAIR1 and HAMAIR1 regdefs, which meant they would UNDEF when the guest tried to access them under cp15. Signed-off-by: Peter Maydell --- A quick grep suggests these are the only ones we got wrong. --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.18.0 Reviewed-by: Edgar E. Iglesias Reviewed-By: Luc Michel diff --git a/target/arm/helper.c b/target/arm/helper.c index 2c5e02c0b1a..466c8ae492e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3767,14 +3767,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, - .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, + .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, - .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, + .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, @@ -3917,7 +3917,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), .resetvalue = 0 }, { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, - .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, + .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, @@ -3926,7 +3926,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .resetvalue = 0 }, /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, - .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, + .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,