From patchwork Tue Aug 14 12:42:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 144161 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4310519ljj; Tue, 14 Aug 2018 05:43:02 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyQgrQTuRLyPQB+CRTngrUjtsq/IQ0hhuDqYiAHz1nPEYKsN3c/SQSJxFraOmQAYwzlLUfL X-Received: by 2002:adf:b3d7:: with SMTP id x23-v6mr13299078wrd.253.1534250582608; Tue, 14 Aug 2018 05:43:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534250582; cv=none; d=google.com; s=arc-20160816; b=zkv/TFnGBzcAOYs81hCqMjd2qgV008UM+HRo9ws4nEuPEdiwsvMay350RNpXvP2Nx4 lYF+AROs0hDkrNpX3aMxeBgirPLyd6tIQMqF1OxJgLYU0KE8J/OrN+dKge0tmej43XNg leX4MLEumL8CspXLMFRHUKWV3QByFlUHmmU1jwYWzohl872hj4QTmt5dSSFbG5cy89zr CbArPCC6PgGzyVp8HXX2eTqWzlAkqVBx4HMKbeRUOsCZsvc4Nfg8Ef8XmDd8eG75uEkZ Lv+aLIM60CZ3XlVk8RRgQeXU99lRP5nUiuFGaMU4iUsdZbQPDkIRLeeskOSLBAc6c49u xlQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Azkn5eXy41NiO7+5yVHVOlgsS+60C6Z2xTtLFfPoiio=; b=s52Xg4IPChwIuH3q64bcpDahcIF7YoEmfnOMBIrSRawCbZfhzJBzMDp91A5PoeBDlr T6+U/Wu6f+oIquOUvDyWJ7OWdu7YjHXP1uo6AKv1TiKMpJr5CvKHk0oLuO2yFHoh2ldV w1mmsUZLhzFRhWuIpb/pOkTOT8wwqsMRfxv222gOdBdnlDGZTANO6YOLXJJ3xjOrjrAp q67IM32jQOe2AGxXBVCEC+t1NAafFks/noLJ8cSlRbqD5wbdVHHHLUg3N3/28Dzr+yNo FQdP4LG94IE0N3g/t2uR9AQwZcKwLcAKeGkYZvky2p0EjtodhvyeL1jQXhaBXZbsMfZl oIjg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id q142-v6si9909028wmb.71.2018.08.14.05.43.02 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 Aug 2018 05:43:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYf8-0006oW-4w; Tue, 14 Aug 2018 13:43:02 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Luc Michel , edgari@xilinx.com Subject: [PATCH 03/10] target/arm: Implement RAZ/WI HACTLR2 Date: Tue, 14 Aug 2018 13:42:47 +0100 Message-Id: <20180814124254.5229-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> The AArch32 HACTLR2 register maps to bits [63:32] of ACTLR_EL2. We implement ACTLR_EL2 as RAZ/WI, so make HACTLR2 also RAZ/WI. (We put the regdef next to ACTLR_EL2 as a reminder in case we ever make ACTLR_EL2 something other than RAZ/WI). Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.18.0 Reviewed-by: Edgar E. Iglesias diff --git a/target/arm/helper.c b/target/arm/helper.c index 466c8ae492e..14fd78f587a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5436,6 +5436,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* HACTLR2 maps to ACTLR_EL2[63:32] */ + { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, + .access = PL2_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, .access = PL3_RW, .type = ARM_CP_CONST,