From patchwork Tue Aug 14 12:42:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 144163 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4310588ljj; Tue, 14 Aug 2018 05:43:06 -0700 (PDT) X-Google-Smtp-Source: AA+uWPwTU5D/CzECliq8g2f+/6PuQKAZ5xw7UsHfjBi7eQIN+uNnGtfNMKRrYedG+D45N8NX3rFi X-Received: by 2002:a1c:588d:: with SMTP id m135-v6mr10283847wmb.118.1534250586230; Tue, 14 Aug 2018 05:43:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534250586; cv=none; d=google.com; s=arc-20160816; b=sJCPLQscfPDjkAwVpTPyQfUdGxJLAvdSlvJGDGn6O9YMm7XX3J9XCtccue/1cZexHB XY54I7wxhBlcvgzx498YAnetIoMthzKjVd20DIH5zxgbrWj8KxoSLK2abrxlb3DyOfjA sRbFpzEr/EN4kEPk0mjtoguXP8upaIdO99hBvwbf/lBTBr4UMJsdT55+qDfFxH/pHR4T vhyz2ztZPhNoAEZXvyEC7LpDAkwIBiVCQ6f68jtL0dhUY4lqZuqGFE4Gpn5u57w2He/3 5G6GEsPOV7sqSTZjVumxvAsMiQuwn5wIFKr8zMNx++6R2+NUpMIieeslyNoZ16yHp0tB HRZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=8MwzJ9f/vxLE1fxiIaPq2ABIdXNCoD1QTj1Ix0bVFW4=; b=klmkTtHU6Nv9M3XBSej/jKYiG4t+uK87PkYHs/R1KAkbs8dZu0CBV8AKfGnRgdAAnB 6hPVfXVXmNmk/xceqse2dhlf1/0Lf8paJ9whDBo3l5Cb5QGIm/4q2WqDO3sPlWMKSG4L oqakFAj9xq0YNcggzP4getmL49rDMGt9Y+XlYKB9hVOitZUJTdw9oMvxcU3RA1YqX/Qj 0fDeNDyLQG/W4VGue+XLw5SCJXsMkzlzvBa7CNU2KUx3U4wdT0mvcsMuKXooLvGPw1F9 6u4/hkISD61Z1ObbQEk0aRD5p01jK48kk873e0IxnHhEKTRJxyXtqX9hjf5Gn61ETG4z c8/w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id o78-v6si10137042wmg.63.2018.08.14.05.43.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 Aug 2018 05:43:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfB-0006pY-Na; Tue, 14 Aug 2018 13:43:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Luc Michel , edgari@xilinx.com Subject: [PATCH 05/10] target/arm: Implement AArch32 HCR and HCR2 Date: Tue, 14 Aug 2018 13:42:49 +0100 Message-Id: <20180814124254.5229-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> The AArch32 HCR and HCR2 registers alias HCR_EL2 bits [31:0] and [63:32]; implement them. Signed-off-by: Peter Maydell --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) -- 2.18.0 Reviewed-by: Edgar E. Iglesias diff --git a/target/arm/helper.c b/target/arm/helper.c index b6412fe9d1f..9701e413859 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3754,11 +3754,15 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, .access = PL2_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, - { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, + { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_NO_RAW, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "HCR2", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, + .access = PL2_RW, + .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -3872,10 +3876,26 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) * HCR_PTW forbids certain page-table setups * HCR_DC Disables stage1 and enables stage2 translation */ - if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { + if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { tlb_flush(CPU(cpu)); } - raw_write(env, ri, value); + env->cp15.hcr_el2 = value; +} + +static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ + value = deposit64(env->cp15.hcr_el2, 32, 32, value); + hcr_write(env, NULL, value); +} + +static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Handle HCR write, i.e. write to low half of HCR_EL2 */ + value = deposit64(env->cp15.hcr_el2, 0, 32, value); + hcr_write(env, NULL, value); } static const ARMCPRegInfo el2_cp_reginfo[] = { @@ -3883,6 +3903,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .writefn = hcr_write }, + { .name = "HCR", .state = ARM_CP_STATE_AA32, + .type = ARM_CP_ALIAS, + .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), + .writefn = hcr_writelow }, + { .name = "HCR2", .state = ARM_CP_STATE_AA32, + .type = ARM_CP_ALIAS, + .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, + .access = PL2_RW, + .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), + .writefn = hcr_writehigh }, { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,