From patchwork Tue Aug 14 12:42:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 144165 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4310630ljj; Tue, 14 Aug 2018 05:43:08 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyyqm2YkpmHFCxwSamb9Iubwu5bJ1IgN5CM68mWyNl2ztcr0d5WRYJiU1mGO9kzy8vqNEr3 X-Received: by 2002:a5d:694e:: with SMTP id r14-v6mr13084072wrw.278.1534250588101; Tue, 14 Aug 2018 05:43:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534250588; cv=none; d=google.com; s=arc-20160816; b=xYPY/FAcauMztyDfCIutsFpmGXp+VdKiB5mMTrnujDdfGaWNSwe9XnNoipp+rbd870 NWrEbfesDt04On4MkcMY6mbV3Ry1t+Nasxvp3+6vhEury+zx+SQm2TUTSUQHrbxpn+MX 2PwgH39tFPwx9MKHrLmVSYVZLYmVFEG5syxoz5fM6etZhl9NmJycZ0c870wiDx4KqH7P IHdJgqrzfPrYFL7Y2KCAjq029CawcKkb2THD2S2Z1v9QE/RqfN/7b5xC1iZOj5y5T9hc uQTqYoeB+WHrMkMCc3+XGuUEwggebBMfOP0dnN/0VheKiMPGOZd/Es+i8ObHQ/jwk/sm Hfew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=vbissEZ+heVMTPzGQaRF1s4znKUPWVhKAMIA1/YnTJ8=; b=wnux/uyDTd4g2ETvyzq8sg6bagO7WbnCnHY+4kLrSXiqRWw16+iTHeJ3Ztyze3dDK8 IkNkcIDiJxak3JMDrAw/3HURuz1gQaajD0esgHIVAJ/gPVU9YqsNavkq2hrgXl8Ol/IU C5VFHrMx1NEkNNhcF7iYtiKNys4UiwzfNxgjQ7oFbEFSNaWfZco5rVGhglgRBtRd1MAR 11myO1+l13iN1kGp/048v3OVYM4tv911hTYz7eD2QAt6iiyDLB2bdMLTyBxOWC7fZYiE d2Eo84iOOqV4gbZr+u7tPsOrgRhTY8oJZEYkamde2es8tC0smD9E5FCP+UpGj58RYh0Z 8iUA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id w66-v6si8432554wmf.64.2018.08.14.05.43.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 Aug 2018 05:43:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfD-0006qa-Jg; Tue, 14 Aug 2018 13:43:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Luc Michel , edgari@xilinx.com Subject: [PATCH 07/10] target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2 Date: Tue, 14 Aug 2018 13:42:51 +0100 Message-Id: <20180814124254.5229-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> The AArch32 HSR is the equivalent of AArch64 ESR_EL2; we can implement it by marking our existing ESR_EL2 regdef as STATE_BOTH. It also needs to be "RES0 from EL3 if EL2 not implemented", so add the missing stanza to el3_no_el2_cp_reginfo. Signed-off-by: Peter Maydell --- target/arm/helper.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.18.0 Reviewed-by: Edgar E. Iglesias Reviewed-By: Luc Michel diff --git a/target/arm/helper.c b/target/arm/helper.c index d6e98e9d606..80855302089 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3763,6 +3763,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, + .access = PL2_RW, + .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -3926,7 +3930,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, - { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, + { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,