From patchwork Tue Aug 21 04:33:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144678 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4792151ljj; Mon, 20 Aug 2018 21:47:01 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyKbHqoyLMlhZtczXzAyfO7efjv4p1wiYcUytUKWQq64U4+POWahChAw8I9KBpXlLAWwPFV X-Received: by 2002:ae9:df81:: with SMTP id t123-v6mr44301383qkf.55.1534826821028; Mon, 20 Aug 2018 21:47:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534826821; cv=none; d=google.com; s=arc-20160816; b=jrGJVJF6A3Xt9toSp8ENWAW/QZPg0QX4NZxEiwMwG+Kae38rR+IupYQjAyi4iWUVna PtfZaKuZcbLp0Q9iEHL2rqM58qAgSGsTUOH3OrGHGwE2Sjl9JttZqX/zyrYsGak1+CFj iPZ+ed78lRHVJpufEWPIVkeOH6fwcvtE3ox81qvtbRsEHCmcOUxw4xtzFa9fKCYcalKm GUrK41Hn99kyH+iwSFS5ohcCJj4ykFI2VZD9ncXK/+p2vueVTeawUekPTxkZInQ9TcTO mIPPnZlRf0rI0iqcBqihWYKNqZQ51+bW0R1wY7o3TL30kk4j0GJ4Yi+5BGR6/94CJC4y EHWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=n0IpqfTDLwrZpq3IEzjOQB6/W2QKG+ZrJ3uMebrzv3o=; b=krT2rC4uukXenmVIwM6PkSXzOMWRbrL65/GF2MhiW76xMIVfeVhCgWReGY83yEngjA ef2dUVHFzdoq6e18klpPuQ5wKZXyNtCnkgDpv8D4ekJ/TH8NqBTmzrFr3UqgLrEii35K 5/mvK3xzooRq/wHZgnMp2nKWS7YG47CB5Rszp8p7+Y7DMFqzhsS4GFDKOye310e60lg8 f9yBNbmQi1yRL6Kb99mbN1oO6ZPYClLUOGYvcWwIWPleThUZmYbLQWZZr+b1FX+SWRmO KE95AuRLOa1JUriH37Nkdzgu4XsUQOA/rm4HN7ooq+7xP6e6IgAoJwWWy0gKGxg3IESW FVow== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=CatbMSuV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 57-v6si9455252qtz.128.2018.08.20.21.47.00 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:47:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=CatbMSuV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50715 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryZI-0000dg-F0 for patch@linaro.org; Tue, 21 Aug 2018 00:47:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMt-0004C1-SV for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMp-0000NM-9o for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:11 -0400 Received: from ozlabs.org ([203.11.71.1]:46965) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMo-0000JH-6U; Tue, 21 Aug 2018 00:34:06 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9G1msRz9sD7; Tue, 21 Aug 2018 14:33:52 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826034; bh=d+8xQmTWasCBYoO3Op9r5ttTiFZD2waYkZal7DNyHh8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CatbMSuVvgJqDyAomf1z+dQZnFceRLFYWgr3NLuI/1QrMYYEX5UpClDzWbq5gAer8 Tpt9ba2dXHCl/9D/HzxIn9y8/wVJqh0Rl/HwSCdGq+8vy+Yr2x3P1bDCFHI5y1Mnnw XeqXZ3qSn2cbj1r3CR9MQmVo85HM2IlArO8AFlzM= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:35 +1000 Message-Id: <20180821043343.7514-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 18/26] hw/ppc/ppc405_uc: Convert away from old_mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Convert the devices in ppc405_uc away from using the old_mmio MemoryRegion accessors: * opba's 32-bit and 16-bit accessors were just calling the 8-bit accessors and assembling a big-endian order number, which we can do by setting the .impl.max_access_size to 1 and the endianness to DEVICE_BIG_ENDIAN, and letting the core memory code do the assembly * ppc405_gpio's accessors were all just stubs * ppc4xx_gpt's 8-bit and 16-bit accessors were treating the access as invalid, which we can do by setting the .valid.min_access_size and .valid.max_access_size fields Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/ppc/ppc405_uc.c | 173 +++++++-------------------------------------- 1 file changed, 25 insertions(+), 148 deletions(-) -- 2.17.1 diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 4bd9fbcc1e..5c58415cf1 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -283,7 +283,7 @@ struct ppc4xx_opba_t { uint8_t pr; }; -static uint32_t opba_readb (void *opaque, hwaddr addr) +static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) { ppc4xx_opba_t *opba; uint32_t ret; @@ -307,8 +307,8 @@ static uint32_t opba_readb (void *opaque, hwaddr addr) return ret; } -static void opba_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ppc4xx_opba_t *opba; @@ -328,61 +328,14 @@ static void opba_writeb (void *opaque, break; } } - -static uint32_t opba_readw (void *opaque, hwaddr addr) -{ - uint32_t ret; - -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - ret = opba_readb(opaque, addr) << 8; - ret |= opba_readb(opaque, addr + 1); - - return ret; -} - -static void opba_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba_writeb(opaque, addr, value >> 8); - opba_writeb(opaque, addr + 1, value); -} - -static uint32_t opba_readl (void *opaque, hwaddr addr) -{ - uint32_t ret; - -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - ret = opba_readb(opaque, addr) << 24; - ret |= opba_readb(opaque, addr + 1) << 16; - - return ret; -} - -static void opba_writel (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba_writeb(opaque, addr, value >> 24); - opba_writeb(opaque, addr + 1, value >> 16); -} - static const MemoryRegionOps opba_ops = { - .old_mmio = { - .read = { opba_readb, opba_readw, opba_readl, }, - .write = { opba_writeb, opba_writew, opba_writel, }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, + .read = opba_readb, + .write = opba_writeb, + .impl.min_access_size = 1, + .impl.max_access_size = 1, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .endianness = DEVICE_BIG_ENDIAN, }; static void ppc4xx_opba_reset (void *opaque) @@ -750,65 +703,27 @@ struct ppc405_gpio_t { uint32_t isr1l; }; -static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr) +static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { #ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); + printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); #endif return 0; } -static void ppc405_gpio_writeb (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif -} - -static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr) +static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { #ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - - return 0; -} - -static void ppc405_gpio_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif -} - -static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - - return 0; -} - -static void ppc405_gpio_writel (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); + printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", + __func__, addr, size, value); #endif } static const MemoryRegionOps ppc405_gpio_ops = { - .old_mmio = { - .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, }, - .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, }, - }, + .read = ppc405_gpio_read, + .write = ppc405_gpio_write, .endianness = DEVICE_NATIVE_ENDIAN, }; @@ -1017,44 +932,6 @@ struct ppc4xx_gpt_t { uint32_t mask[5]; }; -static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - /* XXX: generate a bus fault */ - return -1; -} - -static void ppc4xx_gpt_writeb (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - /* XXX: generate a bus fault */ -} - -static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - /* XXX: generate a bus fault */ - return -1; -} - -static void ppc4xx_gpt_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - /* XXX: generate a bus fault */ -} - static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) { /* XXX: TODO */ @@ -1107,7 +984,7 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) /* XXX: TODO */ } -static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) +static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { ppc4xx_gpt_t *gpt; uint32_t ret; @@ -1162,8 +1039,8 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) return ret; } -static void ppc4xx_gpt_writel (void *opaque, - hwaddr addr, uint32_t value) +static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ppc4xx_gpt_t *gpt; int idx; @@ -1225,10 +1102,10 @@ static void ppc4xx_gpt_writel (void *opaque, } static const MemoryRegionOps gpt_ops = { - .old_mmio = { - .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, }, - .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, }, - }, + .read = ppc4xx_gpt_read, + .write = ppc4xx_gpt_write, + .valid.min_access_size = 4, + .valid.max_access_size = 4, .endianness = DEVICE_NATIVE_ENDIAN, };